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Trivial. Clean up code and add some comments. 

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2010-10-13 02:46:59 +00:00 committed by Zheng Bao
parent 5e9c1cd693
commit 89122856e0
2 changed files with 42 additions and 39 deletions
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12
src/northbridge/amd/amdmct/mct/mctdqs_d.c
View File

@ -509,7 +509,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5);
ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8);
// print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
/* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */
tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */
if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) {
@ -527,7 +527,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
}
if (BanksPresent) {
u8 mask_pass = 0;
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4);
pDCTstat->ByteLane = ByteLane;
@ -572,7 +571,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
}
}
}
print_debug_dqs("\t\t\t\tTrainDQSPos: 41 mask_pass ",mask_pass, 3);
}
skipLocMiddle:
pDCTstat->TrainErrors = Errors;
@ -782,16 +780,16 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
test_buf += 2;
}
bytelane = 0;
bitmap = 0xFF;
for (i=0; i < (9 * 64 / 4); i++) { /* /4 due to next loop */
bytelane = 0; /* bytelane counter */
bitmap = 0xFF; /* bytelane test bitmap, 1=pass */
for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo);
value_test = *test_buf;
print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", value_test, 7);
print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", value, 7);
for (j = 0; j < (4 * 8); j += 8) {
for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */
if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) {
bitmap &= ~(1 << bytelane);
}

21
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
View File

@ -552,7 +552,6 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
}
if (BanksPresent) {
u8 mask_pass = 0;
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4);
if (!(pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane))) {
@ -624,9 +623,8 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
pDCTstat->DqsRdWrPos_Saved |= 1 << ByteLane;
}
}
} /* if (pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane)) */
}
print_debug_dqs("\t\t\t\tTrainDQSPos: 41 mask_pass ",mask_pass, 3);
} /* if (pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane)) */
}
/* skipLocMiddle: */
pDCTstat->TrainErrors = Errors;
@ -853,11 +851,11 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
test_buf += 2;
}
bytelane = 0;
bitmap = 0xFFFF;
bytelane = 0; /* bytelane counter */
bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */
MEn1Results = 0xFFFF;
BeatCnt = 0;
for (i=0; i < (9 * 64 / 4); i++) { /* /4 due to next loop */
for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo);
value_test = *test_buf;
@ -867,7 +865,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
if (pDCTstat->Direction == DQS_READDIR) {
if (BeatCnt != 0) {
value_r = *test_buf;
if (pattern)
if (pattern) /* if multi-channel */
value_r_test = read32_fs(addr_lo - 16);
else
value_r_test = read32_fs(addr_lo - 8);
@ -876,7 +874,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
print_debug_dqs_pair("\t\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value_r = ", value_r_test, 7);
}
for (j = 0; j < (4 * 8); j += 8) {
for (j = 0; j < (4 * 8); j += 8) { /* go through a 32bit data, on 1 byte step. */
if (((value >> j) & 0xff) != ((value_test >> j) & 0xff)) {
bitmap &= ~(1 << bytelane);
}
@ -1079,6 +1077,9 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat,
}
}
/*
* Set DQS delay value to related register
*/
static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 ChipSel)
{
@ -1126,6 +1127,10 @@ static void mct_SetDQSDelayCSR_D(struct MCTStatStruc *pMCTstat,
}
}
/*
* mct_SetDQSDelayAllCSR_D:
* Write the Delay value to all eight byte lanes.
*/
static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat,
u8 cs_start)