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SPD: Add CAS latency 2 

CAS latency = 2 support added for DDR2.

Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15439
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2016-06-26 17:46:21 +02:00 committed by Patrick Georgi
parent 74bb412753
commit 89186b2eb8
1 changed files with 1 additions and 0 deletions
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src/include/spd.h
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@ -147,6 +147,7 @@ enum spd_memory_type {
#define SPD_CAS_LATENCY_3_5 0x20 #define SPD_CAS_LATENCY_3_5 0x20
#define SPD_CAS_LATENCY_4_0 0x40 #define SPD_CAS_LATENCY_4_0 0x40
#define SPD_CAS_LATENCY_DDR2_2 (1 << 2)
#define SPD_CAS_LATENCY_DDR2_3 (1 << 3) #define SPD_CAS_LATENCY_DDR2_3 (1 << 3)
#define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_4 (1 << 4)
#define SPD_CAS_LATENCY_DDR2_5 (1 << 5) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5)