amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should be made in its northbridge code rather than the CPU code. Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8254 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -34,20 +34,6 @@ static void agesawrapper_post_device(void *unused)
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AGESAWRAPPER(amdinitlate);
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#if (1) /* NORTHBRIDGE_00730F01 */
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device_t dev;
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u32 value;
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dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
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pci_write_config32(dev, 0xF8, 0);
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pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
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/* disable No Snoop */
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dev = dev_find_slot(0, PCI_DEVFN(1, 1));
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value = pci_read_config32(dev, 0x60);
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value &= ~(1 << 11);
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pci_write_config32(dev, 0x60, value);
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#endif
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if (!acpi_s3_resume_allowed())
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return;
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@ -635,9 +635,25 @@ static const struct pci_driver family10_northbridge __pci_driver = {
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.device = PCI_DEVICE_ID_AMD_10H_NB_HT,
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};
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static void fam16_finalize(void *chip_info)
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{
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device_t dev;
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u32 value;
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dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
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pci_write_config32(dev, 0xF8, 0);
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pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
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/* disable No Snoop */
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dev = dev_find_slot(0, PCI_DEVFN(1, 1));
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value = pci_read_config32(dev, 0x60);
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value &= ~(1 << 11);
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pci_write_config32(dev, 0x60, value);
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}
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struct chip_operations northbridge_amd_pi_00730F01_ops = {
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CHIP_NAME("AMD FAM16 Northbridge")
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.enable_dev = 0,
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.final = fam16_finalize,
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};
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static void domain_read_resources(device_t dev)
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