amd/00730F01: Move SteppeEagle specific settings to northbridge

These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.

Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Dave Frodin 2015-01-19 15:58:24 -07:00
parent 452efc23b9
commit 891f71a541
2 changed files with 16 additions and 14 deletions

View File

@ -34,20 +34,6 @@ static void agesawrapper_post_device(void *unused)
AGESAWRAPPER(amdinitlate);
#if (1) /* NORTHBRIDGE_00730F01 */
device_t dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);
#endif
if (!acpi_s3_resume_allowed())
return;

View File

@ -635,9 +635,25 @@ static const struct pci_driver family10_northbridge __pci_driver = {
.device = PCI_DEVICE_ID_AMD_10H_NB_HT,
};
static void fam16_finalize(void *chip_info)
{
device_t dev;
u32 value;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
/* disable No Snoop */
dev = dev_find_slot(0, PCI_DEVFN(1, 1));
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);
}
struct chip_operations northbridge_amd_pi_00730F01_ops = {
CHIP_NAME("AMD FAM16 Northbridge")
.enable_dev = 0,
.final = fam16_finalize,
};
static void domain_read_resources(device_t dev)