baytrail: Add ACPI CPU entries
- C-state table based on static config MWAIT values are from ref code for non-S0ix config C6 substate 8 is ignored by the kernel as it violates the CPUID but it is left in as the other substate may not work. - P-state table generated with proper ratio and VID values relies on having the package power msr set to magic value as the power-on default is wrong - T-state table uses static table BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4954 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie
Aaron Durbin
parent
6aa9f1f0eb
commit
8923be58b8
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@ -24,14 +24,56 @@
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#include <arch/smp/mpspec.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <console/console.h>
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#include <types.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/intel/turbo.h>
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#include <baytrail/acpi.h>
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#include <baytrail/iomap.h>
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#include <baytrail/irq.h>
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#include <baytrail/msr.h>
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#include <baytrail/pattrs.h>
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#include <baytrail/pmc.h>
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#define MWAIT_RES(state, sub_state) \
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{ \
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.addrl = (((state) << 4) | (sub_state)), \
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.space_id = ACPI_ADDRESS_SPACE_FIXED, \
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.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
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.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
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.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
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}
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/* C-state map without S0ix */
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static acpi_cstate_t cstate_map[] = {
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{
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/* C1 */
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.ctype = 1, /* ACPI C1 */
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.latency = 1,
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.power = 1000,
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.resource = MWAIT_RES(0, 0),
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},
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{
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/* C6NS with no L2 shrink */
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/* NOTE: this substate is above CPUID limit */
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.ctype = 2, /* ACPI C2 */
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.latency = 500,
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.power = 10,
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.resource = MWAIT_RES(5, 8),
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},
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{
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/* C6FS with full L2 shrink */
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.ctype = 3, /* ACPI C3 */
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.latency = 1500, /* 1.5ms worst case */
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.power = 10,
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.resource = MWAIT_RES(5, 2),
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}
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};
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static int acpi_sci_irq(void)
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{
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const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
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@ -210,7 +252,210 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
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fadt->x_gpe1_blk.resv = 0;
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fadt->x_gpe1_blk.addrl = 0x0;
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fadt->x_gpe1_blk.addrh = 0x0;
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}
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static acpi_tstate_t baytrail_tss_table[] = {
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{ 100, 1000, 0, 0x00, 0 },
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{ 88, 875, 0, 0x1e, 0 },
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{ 75, 750, 0, 0x1c, 0 },
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{ 63, 625, 0, 0x1a, 0 },
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{ 50, 500, 0, 0x18, 0 },
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{ 38, 375, 0, 0x16, 0 },
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{ 25, 250, 0, 0x14, 0 },
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{ 13, 125, 0, 0x12, 0 },
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};
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static int generate_T_state_entries(int core, int cores_per_package)
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{
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int len;
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/* Indicate SW_ALL coordination for T-states */
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len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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/* Indicate FFixedHW so OS will use MSR */
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len += acpigen_write_empty_PTC();
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/* Set NVS controlled T-state limit */
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len += acpigen_write_TPC("\\TLVL");
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/* Write TSS table for MSR access */
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len += acpigen_write_TSS_package(
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ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
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return len;
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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{
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u32 m;
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u32 power;
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/*
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* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
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*
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* Power = (ratio / p1_ratio) * m * tdp
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*/
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m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
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m = (m * m) / 1000;
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power = ((ratio * 100000 / p1_ratio) / 100);
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power *= (m / 100) * (tdp / 1000);
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power /= 1000;
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return (int)power;
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}
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static int generate_P_state_entries(int core, int cores_per_package)
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{
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int len, len_pss;
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int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
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int coord_type, power_max, power_unit, num_entries;
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int ratio, power, clock, clock_max;
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int vid, vid_turbo, vid_min, vid_max, vid_range_2;
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u32 control_status;
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const struct pattrs *pattrs = pattrs_get();
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msr_t msr;
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/* Inputs from CPU attributes */
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ratio_max = pattrs->iacore_ratios[IACORE_MAX];
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ratio_min = pattrs->iacore_ratios[IACORE_LFM];
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vid_max = pattrs->iacore_vids[IACORE_MAX];
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vid_min = pattrs->iacore_vids[IACORE_LFM];
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/* Hardware coordination of P-states */
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coord_type = HW_ALL;
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/* Max Non-Turbo Frequency */
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clock_max = (ratio_max * pattrs->bclk_khz) / 1000;
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/* Calculate CPU TDP in mW */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 1 << (msr.lo & 0xf);
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msr = rdmsr(MSR_PKG_POWER_LIMIT);
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power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC(0);
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, 1, coord_type);
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/* Add P-state entries in _PSS table */
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len += acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = 1;
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num_entries = (ratio_max - ratio_min) / ratio_step;
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while (num_entries > 15) { /* ACPI max is 15 ratios */
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ratio_step <<= 1;
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num_entries >>= 1;
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}
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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len_pss = acpigen_write_package(num_entries + 2);
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ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
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vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
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control_status = (ratio_turbo << 8) | vid_turbo;
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/* Add entry for Turbo ratio */
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len_pss += acpigen_write_PSS_package(
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clock_max + 1, /*MHz*/
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power_max, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control*/
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control_status); /*status*/
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} else {
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/* _PSS package count without Turbo */
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len_pss = acpigen_write_package(num_entries + 1);
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ratio_turbo = ratio_max;
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vid_turbo = vid_max;
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}
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/* First regular entry is max non-turbo ratio */
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control_status = (ratio_max << 8) | vid_max;
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len_pss += acpigen_write_PSS_package(
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clock_max, /*MHz*/
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power_max, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control */
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control_status); /*status*/
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/* Set up ratio and vid ranges for VID calculation */
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ratio_range_2 = (ratio_turbo - ratio_min) * 2;
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vid_range_2 = (vid_turbo - vid_min) * 2;
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/* Generate the remaining entries */
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for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
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ratio >= ratio_min; ratio -= ratio_step) {
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/* Calculate VID for this ratio */
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vid = ((ratio - ratio_min) * vid_range_2) /
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ratio_range_2 + vid_min;
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/* Round up if remainder */
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if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
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vid++;
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = (ratio * pattrs->bclk_khz) / 1000;
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control_status = (ratio << 8) | (vid & 0xff);
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len_pss += acpigen_write_PSS_package(
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clock, /*MHz*/
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power, /*mW*/
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10, /*lat1*/
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10, /*lat2*/
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control_status, /*control*/
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control_status); /*status*/
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}
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/* Fix package length */
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len_pss--;
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acpigen_patch_len(len_pss);
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return len + len_pss;
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}
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void generate_cpu_entries(void)
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{
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int len_pr, core;
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int pcontrol_blk = get_pmbase(), plen = 6;
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const struct pattrs *pattrs = pattrs_get();
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for (core=0; core<pattrs->num_cpus; core++) {
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if (core > 0) {
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pcontrol_blk = 0;
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plen = 0;
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}
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/* Generate processor \_PR.CPUx */
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len_pr = acpigen_write_processor(
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core, pcontrol_blk, plen);
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/* Generate P-state tables */
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len_pr += generate_P_state_entries(
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core, pattrs->num_cpus);
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/* Generate C-state tables */
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len_pr += acpigen_write_CST_package(
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cstate_map, ARRAY_SIZE(cstate_map));
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/* Generate T-state tables */
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len_pr += generate_T_state_entries(
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core, pattrs->num_cpus);
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len_pr--;
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acpigen_patch_len(len_pr);
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}
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}
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unsigned long acpi_madt_irq_overrides(unsigned long current)
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@ -50,6 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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PCNT, 8, // 0x11 - Processor count
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TPMP, 8, // 0x12 - TPM Present and Enabled
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TLVL, 8, // 0x13 - Throttle Level
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/* Device Config */
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Offset (0x20),
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@ -36,7 +36,8 @@ typedef struct {
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u8 pwrs; /* 0x10 - Power state (AC = 1) */
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u8 pcnt; /* 0x11 - Processor Count */
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u8 tpmp; /* 0x12 - TPM Present and Enabled */
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u8 rsvd1[13];
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u8 tlvl; /* 0x13 - Throttle Level */
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u8 rsvd1[12];
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/* Device Config */
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u8 s5u0; /* 0x20 - Enable USB0 in S5 */
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@ -5,8 +5,6 @@
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#include <baytrail/acpi.h>
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void generate_cpu_entries(void) {}
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void smm_init(void) {}
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/* Rmodules don't like weak symbols. */
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