IEI PM-LX2-800-R10: Added preliminary mainboard support
Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050662496936266123&id=09034367569861123956 Support for the IT8888 PCI to ISA bridge will be added in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins@gmail.com> Reviewed-on: http://review.coreboot.org/1152 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ricardo Martins
Stefan Reinauer
parent
aa5eae629f
commit
892d8d2c58
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@ -31,6 +31,8 @@ config BOARD_IEI_PCISA_LX_800_R10
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bool "PCISA LX-800-R10"
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config BOARD_IEI_PM_LX_800_R11
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bool "PM LX-800-R11"
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config BOARD_IEI_PM_LX2_800_R10
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bool "PM LX2-800-R10"
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endchoice
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@ -39,6 +41,7 @@ source "src/mainboard/iei/kino-780am2-fam10/Kconfig"
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source "src/mainboard/iei/nova4899r/Kconfig"
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source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig"
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source "src/mainboard/iei/pm-lx-800-r11/Kconfig"
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source "src/mainboard/iei/pm-lx2-800-r10/Kconfig"
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config MAINBOARD_VENDOR
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string
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@ -0,0 +1,54 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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if BOARD_IEI_PM_LX2_800_R10
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_AMD_GEODE_LX
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select NORTHBRIDGE_AMD_LX
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select SOUTHBRIDGE_AMD_CS5536
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select SUPERIO_SMSC_SMSCSUPERIO
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select HAVE_PIRQ_TABLE
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select PIRQ_ROUTE
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select BOARD_ROMSIZE_KB_512
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select POWER_BUTTON_FORCE_ENABLE
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select PLL_MANUAL_CONFIG
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select CORE_GLIU_500_266
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config MAINBOARD_DIR
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string
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default iei/pm-lx2-800-r10
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config MAINBOARD_PART_NUMBER
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string
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default "PM-LX2-800-R10"
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config IRQ_SLOT_COUNT
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int
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default 3
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config PLLMSRlo
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hex
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default 0x07de0000
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endif # BOARD_IEI_PM_LX2_800_R10
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@ -0,0 +1,87 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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chip northbridge/amd/lx
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device pci_domain 0 on
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device pci 1.0 on end # Northbridge
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device pci 1.1 on end # Video Adapter
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device pci 1.2 on end # AES Security Block
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chip southbridge/amd/cs5536
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register "lpc_serirq_enable" = "0x000010da"
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register "lpc_serirq_polarity" = "0x0000ef25"
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register "lpc_serirq_mode" = "1"
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register "enable_gpio_int_route" = "0x0d0c0700"
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register "enable_ide_nand_flash" = "0"
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register "enable_USBP4_device" = "0" # 0:host, 1:device
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register "enable_USBP4_overcurrent" = "0"
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register "com1_enable" = "0"
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register "com2_enable" = "0"
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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device pci 11.0 on end # IT8888
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device pci e.0 on end # RTL8100C
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device pci f.0 on # ISA Bridge
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chip superio/smsc/smscsuperio # SMSC SCH3114
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 on # PS/2 keyboard/mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # Keyboard
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irq 0x72 = 12 # Mouse
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end
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device pnp 2e.a on # Runtime Register
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io 0x60 = 0x400
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end
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end
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end
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/geode_lx
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device lapic 0 on end
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end
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end
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end
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@ -0,0 +1,134 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/pci_ids.h>
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#include <arch/pirq_routing.h>
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/* Platform IRQs */
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#define PIRQA 10
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#define PIRQB 10
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#define PIRQC 11
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#define PIRQD 11
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/* Links */
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#define L_PIRQN 0
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#define L_PIRQA 1
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#define L_PIRQB 2
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#define L_PIRQC 3
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#define L_PIRQD 4
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/* Bitmaps */
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#define B_LINKN (0)
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#define B_LINK0 (1 << PIRQA)
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#define B_LINK1 (1 << PIRQB)
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#define B_LINK2 (1 << PIRQC)
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#define B_LINK3 (1 << PIRQD)
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x0f << 3) | 0x0, /* Interrupt router dev */
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(B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3),/* IRQs devoted exclusively to PCI usage */
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PCI_VENDOR_ID_AMD, /* Vendor */
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PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
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0, /* Miniport */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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0x27, /* Checksum */
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{
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[0] = { /* Host bridge */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x01 << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQA,
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.bitmap = B_LINK0
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},
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[1] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[2] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[3] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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}
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}
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},
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[1] = { /* ISA bridge */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x0f << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[1] = {
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.link = L_PIRQB,
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.bitmap = B_LINK1
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},
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[2] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[3] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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}
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}
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},
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[2] = { /* Ethernet */
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.slot = 0x00,
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.bus = 0x00,
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.devfn = (0x0e << 3) | 0x0,
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.irq = {
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[0] = {
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.link = L_PIRQD,
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.bitmap = B_LINK3
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},
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[1] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[2] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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},
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[3] = {
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.link = L_PIRQN,
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.bitmap = B_LINKN
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}
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}
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}
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,52 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/device.h>
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#include <boot/tables.h>
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/* SCH3114 runtime register (RTR) address. */
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#define SCH3114_RTR_ADDR (0x400)
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/* H/W Monitoring register block index. */
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#define SCH3114_RTR_HWM_IDX (SCH3114_RTR_ADDR + 0x70)
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/* H/W Monitoring register block data. */
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#define SCH3114_RTR_HWM_DAT (SCH3114_RTR_ADDR + 0x71)
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/* H/W Monitoring Ready/Lock/Start register. */
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#define SCH3114_HWM_RLS_REG (0x40)
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static void init(struct device *dev)
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{
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/* SCH3114: enable hardware monitor. */
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printk(BIOS_INFO, "Enabling SCH3114 hardware monitor\n");
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outb(SCH3114_HWM_RLS_REG, SCH3114_RTR_HWM_IDX);
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outb(inb(SCH3114_RTR_HWM_DAT) | 0x01, SCH3114_RTR_HWM_DAT);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("IEI PM-LX2-800-R10 Mainboard")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,90 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <spd.h>
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#include <arch/io.h>
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#include <arch/hlt.h>
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#include <arch/llshell.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include <southbridge/amd/cs5536/cs5536.h>
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#include <southbridge/amd/cs5536/early_smbus.c>
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#include <southbridge/amd/cs5536/early_setup.c>
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#include <superio/smsc/smscsuperio/early_serial.c>
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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/* Only DIMM0 is available. */
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if (device != DIMM0)
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return 0xFF;
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return smbus_read_byte(device, address);
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}
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#include <northbridge/amd/lx/raminit.h>
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#include <northbridge/amd/lx/pll_reset.c>
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#include <northbridge/amd/lx/raminit.c>
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#include <lib/generic_sdram.c>
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#include <cpu/amd/geode_lx/cpureginit.c>
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#include <cpu/amd/geode_lx/syspreinit.c>
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#include <cpu/amd/geode_lx/msrinit.c>
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void main(unsigned long bist)
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{
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static const struct mem_controller memctrl[] = {
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{.channel0 = {DIMM0, DIMM1}}
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};
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SystemPreInit();
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msr_init();
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cs5536_early_setup();
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smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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/* Enable COM3. */
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device_t dev = PNP_DEV(0x2e, 0x0b);
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u16 port = dev >> 8;
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outb(0x55, port);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
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pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
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pnp_set_enable(dev, 1);
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outb(0xaa, port);
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report_bist_failure(bist);
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pll_reset();
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cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
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sdram_initialize(1, memctrl);
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}
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