diff --git a/src/southbridge/intel/i82801bx/i82801bx.c b/src/southbridge/intel/i82801bx/i82801bx.c
index 99d630fa77..163b6f4ea4 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.c
+++ b/src/southbridge/intel/i82801bx/i82801bx.c
@@ -21,10 +21,10 @@
 #include <device/pci.h>
 #include "i82801bx.h"
 
-void i82801bx_enable(device_t dev)
+void i82801bx_enable(struct device *dev)
 {
 	u16 reg16, index;
-	device_t lpc_dev;
+	struct device *lpc_dev;
 
 	/* Search for the 82801BA/BAM LPC device (D31:F0) on PCI bus 0. */
 	lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 3ecfe72947..7a6497946b 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -19,7 +19,7 @@
 
 #if !defined(__PRE_RAM__)
 #include "chip.h"
-extern void i82801bx_enable(device_t dev);
+extern void i82801bx_enable(struct device *dev);
 #endif
 
 #if defined(__PRE_RAM__)
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 0d8ebe089a..4fbc0044ab 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -119,7 +119,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev)
 	/* TODO: Explain/#define the real meaning of these magic numbers. */
 }
 
-static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
+static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model)
 {
 	u8 reg8;
 	config_t *config = dev->chip_info;
@@ -150,7 +150,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
 	pci_write_config8(dev, PIRQH_ROUT, reg8);
 }
 
-static void i82801bx_power_options(device_t dev)
+static void i82801bx_power_options(struct device *dev)
 {
 	uint8_t byte;
 	int pwr_on = -1;
@@ -180,7 +180,7 @@ static void i82801bx_power_options(device_t dev)
 	}
 }
 
-static void gpio_init(device_t dev)
+static void gpio_init(struct device *dev)
 {
 	/* Set the value for GPIO base address register and enable GPIO. */
 	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
@@ -222,7 +222,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
 	pci_write_config16(dev, PCI_DMA_CFG, reg16);
 }
 
-static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
+static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model)
 {
 	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
 	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
@@ -269,7 +269,7 @@ static void lpc_init(struct device *dev)
 	i82801bx_lpc_decode_en(dev, ich_model);
 }
 
-static void i82801bx_lpc_read_resources(device_t dev)
+static void i82801bx_lpc_read_resources(struct device *dev)
 {
 	struct resource *res;
 
diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c
index 01e8c373e6..90975cd53d 100644
--- a/src/southbridge/intel/i82801bx/smbus.c
+++ b/src/southbridge/intel/i82801bx/smbus.c
@@ -22,7 +22,7 @@
 #include <southbridge/intel/common/smbus.h>
 #include "i82801bx.h"
 
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
 {
 	u16 device;
 	struct resource *res;
diff --git a/src/southbridge/intel/i82801bx/watchdog.c b/src/southbridge/intel/i82801bx/watchdog.c
index 60a7b57b6c..d0af76c030 100644
--- a/src/southbridge/intel/i82801bx/watchdog.c
+++ b/src/southbridge/intel/i82801bx/watchdog.c
@@ -24,7 +24,7 @@
 
 void watchdog_off(void)
 {
-	device_t dev;
+	struct device *dev;
 	unsigned long value, base;
 
 	/* Turn off the ICH5 watchdog. */