GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

{sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits 

We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.

Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2020-07-25 02:46:39 +02:00 committed by Patrick Georgi
parent 4d2db06ab5
commit 89739baf53
18 changed files with 39 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/baytrail/gfx.c
View File

@ -205,7 +205,7 @@ static const struct reg_script gfx_init_script[] = {
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
/* Display */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,

3
src/soc/intel/baytrail/lpss.c
View File

@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
REG_PCI_OR16(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),

2
src/soc/intel/baytrail/romstage/raminit.c
View File

@ -36,7 +36,7 @@ int smbus_enable_iobar(uintptr_t base)
pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg);
/* Enable decode of I/O space. */
reg = pci_read_config16(smbus_dev, PCI_COMMAND);
reg |= 0x1;
reg |= PCI_COMMAND_IO;
pci_write_config16(smbus_dev, PCI_COMMAND, reg);
/* Enable Host Controller */
reg = pci_read_config8(smbus_dev, 0x40);

2
src/soc/intel/baytrail/scc.c
View File

@ -74,7 +74,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),

2
src/soc/intel/braswell/gfx.c
View File

@ -14,7 +14,7 @@
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY),
REG_SCRIPT_END
};

3
src/soc/intel/braswell/lpss.c
View File

@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
REG_PCI_OR16(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),

3
src/soc/intel/broadwell/sata.c
View File

@ -36,7 +36,8 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */

4
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -520,7 +520,9 @@ static void lpc_init(struct device *dev)
report_pch_info(dev);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);

3
src/southbridge/intel/bd82x6x/sata.c
View File

@ -108,7 +108,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* AHCI */
if (sata_mode == 0) {

4
src/southbridge/intel/i82801dx/lpc.c
View File

@ -253,7 +253,9 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
i82801dx_enable_acpi(dev);
/* IO APIC initialization. */

4
src/southbridge/intel/i82801gx/lpc.c
View File

@ -347,7 +347,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801gx_enable_ioapic(dev);

3
src/southbridge/intel/i82801gx/sata.c
View File

@ -88,7 +88,8 @@ static void sata_init(struct device *dev)
ports = get_ich7_sata_ports();
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
switch (config->sata_mode) {
case SATA_MODE_IDE_LEGACY_COMBINED:

4
src/southbridge/intel/i82801ix/lpc.c
View File

@ -357,7 +357,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801ix_enable_apic(dev);

4
src/southbridge/intel/i82801jx/lpc.c
View File

@ -361,7 +361,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801jx_enable_apic(dev);

4
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -439,7 +439,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);

3
src/southbridge/intel/ibexpeak/sata.c
View File

@ -49,7 +49,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (sata_mode == 0) {
/* AHCI */

4
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -505,7 +505,9 @@ static void lpc_init(struct device *dev)
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);

3
src/southbridge/intel/lynxpoint/sata.c
View File

@ -41,7 +41,8 @@ static void sata_init(struct device *dev)
/* SATA configuration */
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (config->ide_legacy_combined) {
printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");