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mb/google/brask/variants/moli: update emmc_rtd3 enable gpio pin 

EN_PP3300_EMMC has be changed to GPP_A21 for DP++ and it based on Moli GPIO Table_20220803.xlsx, so update enable_gpio for emmc_rtd3 by board_ver.

BUG=b:241370405
TEST=emerge-brask coreboot

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I129706861fd1fcf061371ce94352331ef44359d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Raihow Shi 2022-09-20 18:35:10 +08:00 committed by Felix Held
parent 07192dc7f5
commit 8993fc82ff
1 changed files with 15 additions and 0 deletions
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15
src/mainboard/google/brya/variants/moli/ramstage.c
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@ -11,6 +11,20 @@
#include <fw_config.h>
#include <intelblocks/power_limit.h>
#include <drivers/intel/dptf/chip.h>
#include <boardid.h>
#include <soc/intel/common/block/pcie/rtd3/chip.h>
#include <acpi/acpi_device.h>
static void devtree_update_emmc_rtd3(void)
{
uint32_t board_ver = board_id();
struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
struct soc_intel_common_block_pcie_rtd3_config *config = emmc_rtd3->chip_info;
if (board_ver <= 1)
return;
config->enable_gpio = (struct acpi_gpio) ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21);
}
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
@ -65,6 +79,7 @@ const struct psys_config psys_config = {
void variant_devtree_update(void)
{
devtree_update_emmc_rtd3();
size_t total_entries = ARRAY_SIZE(limits);
variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
variant_update_power_limits(limits, total_entries);