mb/google/brask/variants/moli: update emmc_rtd3 enable gpio pin
EN_PP3300_EMMC has be changed to GPP_A21 for DP++ and it based on Moli GPIO Table_20220803.xlsx, so update enable_gpio for emmc_rtd3 by board_ver. BUG=b:241370405 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I129706861fd1fcf061371ce94352331ef44359d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -11,6 +11,20 @@
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#include <fw_config.h>
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#include <fw_config.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/power_limit.h>
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#include <drivers/intel/dptf/chip.h>
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#include <drivers/intel/dptf/chip.h>
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#include <boardid.h>
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#include <soc/intel/common/block/pcie/rtd3/chip.h>
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#include <acpi/acpi_device.h>
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static void devtree_update_emmc_rtd3(void)
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{
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uint32_t board_ver = board_id();
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struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
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struct soc_intel_common_block_pcie_rtd3_config *config = emmc_rtd3->chip_info;
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if (board_ver <= 1)
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return;
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config->enable_gpio = (struct acpi_gpio) ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21);
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}
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const struct cpu_power_limits limits[] = {
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const struct cpu_power_limits limits[] = {
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/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
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/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
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@ -65,6 +79,7 @@ const struct psys_config psys_config = {
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void variant_devtree_update(void)
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void variant_devtree_update(void)
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{
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{
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devtree_update_emmc_rtd3();
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size_t total_entries = ARRAY_SIZE(limits);
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size_t total_entries = ARRAY_SIZE(limits);
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variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
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variant_update_psys_power_limits(limits, sys_limits, total_entries, &psys_config);
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variant_update_power_limits(limits, total_entries);
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variant_update_power_limits(limits, total_entries);
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