intel/skylake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if it has been set in NVS. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on glados and chell Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313824 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -61,6 +61,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
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GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
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DPTE, 8, // 0x30 - Enable DPTF
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NHLA, 64, // 0x31 - NHLT Address
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NHLL, 32, // 0x39 - NHLT Length
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/* ChromeOS specific */
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Offset (0x100),
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@ -30,6 +30,9 @@
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/* LPC 0:1f.0 */
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#include "lpc.asl"
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/* PCH HDA */
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#include "pch_hda.asl"
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/* PCIE Ports */
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#include "pcie.asl"
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@ -0,0 +1,88 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* Audio Controller - Device 31, Function 3 */
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Device (HDAS)
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{
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Name (_ADR, 0x001F0003)
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Name (_DDN, "Audio Controller")
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Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
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/* Device is D3 wake capable */
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Name (_S0W, 3)
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/* NHLT Table Address populated from GNVS values */
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Name (NBUF, ResourceTemplate () {
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QWordMemory (ResourceConsumer, PosDecode, MinFixed,
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MaxFixed, NonCacheable, ReadOnly,
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0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
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})
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (LEqual (Arg0, ^UUID)) {
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/*
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* Function 0: Function Support Query
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* Returns a bitmask of functions supported.
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*/
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If (LEqual (Arg2, Zero)) {
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/*
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* NHLT Query only supported for revision 1 and
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* if NHLT address and length are set in NVS.
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*/
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If (LAnd (LEqual (Arg1, One),
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LAnd (LNotEqual (NHLA, Zero),
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LNotEqual (NHLL, Zero)))) {
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Return (Buffer (One) { 0x03 })
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} Else {
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Return (Buffer (One) { 0x01 })
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}
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}
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/*
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* Function 1: Query NHLT memory address used by
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* Intel Offload Engine Driver to discover any non-HDA
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* devices that are supported by the DSP.
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*
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* Returns a pointer to NHLT table in memory.
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*/
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If (LEqual (Arg2, One)) {
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CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
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CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
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CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
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Store (NHLA, NBAS)
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Store (NHLA, NMAS)
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Store (NHLL, NLEN)
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Return (NBUF)
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}
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}
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Return (Buffer (One) { 0x00 })
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}
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}
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@ -51,8 +51,9 @@ typedef struct {
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u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
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u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
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u8 dpte; /* 0x30 - Enable DPTF */
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u8 unused[207];
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u64 nhla; /* 0x31 - NHLT Address */
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u32 nhll; /* 0x39 - NHLT Length */
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u8 unused[195];
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/* ChromeOS specific (0x100 - 0xfff) */
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chromeos_acpi_t chromeos;
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