intel/skylake: Add ACPI device for audio controller

Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if it has been set in NVS.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on glados and chell

Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d
Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313824
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2015-11-21 18:40:19 -08:00 committed by Patrick Georgi
parent 21cc96cacd
commit 8996084f82
4 changed files with 96 additions and 2 deletions

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@ -61,6 +61,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
DPTE, 8, // 0x30 - Enable DPTF
NHLA, 64, // 0x31 - NHLT Address
NHLL, 32, // 0x39 - NHLT Length
/* ChromeOS specific */
Offset (0x100),

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@ -30,6 +30,9 @@
/* LPC 0:1f.0 */
#include "lpc.asl"
/* PCH HDA */
#include "pch_hda.asl"
/* PCIE Ports */
#include "pcie.asl"

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@ -0,0 +1,88 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
/* Audio Controller - Device 31, Function 3 */
Device (HDAS)
{
Name (_ADR, 0x001F0003)
Name (_DDN, "Audio Controller")
Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
/* Device is D3 wake capable */
Name (_S0W, 3)
/* NHLT Table Address populated from GNVS values */
Name (NBUF, ResourceTemplate () {
QWordMemory (ResourceConsumer, PosDecode, MinFixed,
MaxFixed, NonCacheable, ReadOnly,
0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
})
/*
* Device Specific Method
* Arg0 - UUID
* Arg1 - Revision
* Arg2 - Function Index
*/
Method (_DSM, 4)
{
If (LEqual (Arg0, ^UUID)) {
/*
* Function 0: Function Support Query
* Returns a bitmask of functions supported.
*/
If (LEqual (Arg2, Zero)) {
/*
* NHLT Query only supported for revision 1 and
* if NHLT address and length are set in NVS.
*/
If (LAnd (LEqual (Arg1, One),
LAnd (LNotEqual (NHLA, Zero),
LNotEqual (NHLL, Zero)))) {
Return (Buffer (One) { 0x03 })
} Else {
Return (Buffer (One) { 0x01 })
}
}
/*
* Function 1: Query NHLT memory address used by
* Intel Offload Engine Driver to discover any non-HDA
* devices that are supported by the DSP.
*
* Returns a pointer to NHLT table in memory.
*/
If (LEqual (Arg2, One)) {
CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
Store (NHLA, NBAS)
Store (NHLA, NMAS)
Store (NHLL, NLEN)
Return (NBUF)
}
}
Return (Buffer (One) { 0x00 })
}
}

View File

@ -51,8 +51,9 @@ typedef struct {
u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
u8 dpte; /* 0x30 - Enable DPTF */
u8 unused[207];
u64 nhla; /* 0x31 - NHLT Address */
u32 nhll; /* 0x39 - NHLT Length */
u8 unused[195];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;