From 8996b277abcdf8eb9d99f302dd3dddab5633a465 Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Fri, 12 Mar 2021 12:52:42 -0700
Subject: [PATCH] mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES

This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/adlrvp/Kconfig | 16 +---------------
 1 file changed, 1 insertion(+), 15 deletions(-)

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 295b56fa58..a359d62145 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -2,6 +2,7 @@ if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M |
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
+	select ADL_ENABLE_USB4_PCIE_RESOURCES
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -84,21 +85,6 @@ config ADL_INTEL_EC
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT
 endchoice
 
-config PCIEXP_HOTPLUG
-	default y
-
-config PCIEXP_HOTPLUG_BUSES
-	int
-	default 42
-
-config PCIEXP_HOTPLUG_MEM
-	hex
-	default 0xc200000  # 194 MiB
-
-config PCIEXP_HOTPLUG_PREFETCH_MEM
-	hex
-	default 0x1c000000 # 448 MiB
-
 config VBOOT
 	select VBOOT_LID_SWITCH
 	select VBOOT_MOCK_SECDATA