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src: Drop unused include <arch/acpi.h> 

Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Elyes HAOUAS 2019-03-04 17:49:46 +01:00 committed by Patrick Georgi
parent c2209e4bef
commit 89989cf61f
50 changed files with 0 additions and 52 deletions
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1
src/cpu/amd/pi/00630F01/model_15_init.c
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@ -26,7 +26,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <arch/acpi.h>
static void model_15_init(struct device *dev) static void model_15_init(struct device *dev)
{ {

1
src/cpu/amd/pi/00660F01/model_15_init.c
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@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <arch/acpi.h>
#include <amdlib.h> #include <amdlib.h>
#include <PspBaseLib.h> #include <PspBaseLib.h>

1
src/cpu/amd/pi/00730F01/model_16_init.c
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@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <arch/acpi.h>
static void model_16_init(struct device *dev) static void model_16_init(struct device *dev)
{ {

1
src/cpu/intel/haswell/romstage.c
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@ -24,7 +24,6 @@
#include <halt.h> #include <halt.h>
#include <lib.h> #include <lib.h>
#include <timestamp.h> #include <timestamp.h>
#include <arch/acpi.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cbmem.h> #include <cbmem.h>

1
src/cpu/x86/mtrr/mtrr.c
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@ -33,7 +33,6 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <memrange.h> #include <memrange.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <assert.h> #include <assert.h>

1
src/mainboard/amd/bettong/mainboard.c
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@ -15,7 +15,6 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/acpi.h>
#include <agesawrapper.h> #include <agesawrapper.h>
#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/common/amd_pci_util.h>

1
src/mainboard/amd/db-ft3b-lc/mainboard.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>

1
src/mainboard/amd/gardenia/mainboard.c
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@ -15,7 +15,6 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/acpi.h>
#include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h> #include <amdblocks/amd_pci_util.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>

1
src/mainboard/amd/lamar/mainboard.c
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@ -17,7 +17,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>
#include <northbridge/amd/pi/00630F01/pci_devs.h> #include <northbridge/amd/pi/00630F01/pci_devs.h>

1
src/mainboard/amd/olivehillplus/mainboard.c
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@ -17,7 +17,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>

1
src/mainboard/amd/thatcher/romstage.c
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <commonlib/loglevel.h> #include <commonlib/loglevel.h>

1
src/mainboard/asrock/imb-a180/romstage.c
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <commonlib/loglevel.h> #include <commonlib/loglevel.h>

1
src/mainboard/asus/p5gc-mx/romstage.c
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@ -24,7 +24,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/bap/ode_e21XX/mainboard.c
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@ -17,7 +17,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h> #include <cpu/amd/mtrr.h>

1
src/mainboard/getac/p470/romstage.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>

1
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/intel/bayleybay_fsp/mainboard.c
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@ -22,7 +22,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <arch/acpi.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

1
src/mainboard/intel/bayleybay_fsp/romstage.c
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@ -24,7 +24,6 @@
#include <soc/lpc.h> #include <soc/lpc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <soc/acpi.h>
#include <soc/baytrail.h> #include <soc/baytrail.h>
#include <drivers/intel/fsp1_0/fsp_util.h> #include <drivers/intel/fsp1_0/fsp_util.h>

1
src/mainboard/intel/camelbackmountain_fsp/mainboard.c
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@ -22,7 +22,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <arch/acpi.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

1
src/mainboard/intel/dcp847ske/early_southbridge.c
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@ -21,7 +21,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

1
src/mainboard/intel/emeraldlake2/romstage.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <superio/smsc/sio1007/chip.h> #include <superio/smsc/sio1007/chip.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>

1
src/mainboard/intel/kblrvp/smihandler.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <elog.h> #include <elog.h>

1
src/mainboard/kontron/ktqm77/mainboard.c
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@ -25,7 +25,6 @@
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/kontron/ktqm77/romstage.c
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <arch/acpi.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>

1
src/mainboard/lenovo/t60/romstage.c
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@ -25,7 +25,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

1
src/mainboard/lenovo/x1_carbon_gen1/romstage.c
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@ -23,7 +23,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

1
src/mainboard/lenovo/x230/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>

1
src/mainboard/lippert/frontrunner-af/mainboard.c
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@ -22,7 +22,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h> #include <southbridge/amd/sb800/sb800.h>
#include <arch/acpi.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
#include <southbridge/amd/cimx/sb800/gpio_oem.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h>

1
src/mainboard/lippert/toucan-af/mainboard.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h> #include <southbridge/amd/sb800/sb800.h>
#include <arch/acpi.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */
#include <southbridge/amd/cimx/sb800/gpio_oem.h> #include <southbridge/amd/cimx/sb800/gpio_oem.h>

1
src/mainboard/pcengines/apu1/mainboard.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/cimx_util.h> #include <southbridge/amd/cimx/cimx_util.h>
#include <arch/acpi.h>
#include <smbios.h> #include <smbios.h>
#include <string.h> #include <string.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>

1
src/mainboard/pcengines/apu2/mainboard.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>

1
src/mainboard/roda/rk886ex/romstage.c
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@ -23,7 +23,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>

1
src/mainboard/samsung/lumpy/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cbfs.h> #include <cbfs.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <bootmode.h> #include <bootmode.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>

1
src/mainboard/samsung/stumpy/romstage.c
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@ -21,7 +21,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <bootmode.h> #include <bootmode.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>

1
src/mainboard/siemens/mc_bdx1/mainboard.c
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@ -26,7 +26,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <arch/acpi.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

1
src/mainboard/siemens/mc_tcu3/mainboard.c
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@ -22,7 +22,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <arch/acpi.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <hwilib.h> #include <hwilib.h>

1
src/northbridge/intel/gm45/iommu.c
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@ -19,7 +19,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/acpi.h>
#include "gm45.h" #include "gm45.h"

1
src/northbridge/intel/gm45/northbridge.c
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@ -27,7 +27,6 @@
#include <cpu/intel/smm/gen1/smi.h> #include <cpu/intel/smm/gen1/smi.h>
#include "chip.h" #include "chip.h"
#include "gm45.h" #include "gm45.h"
#include "arch/acpi.h"
/* Reserve segments A and B: /* Reserve segments A and B:
* *

1
src/northbridge/intel/i945/early_init.c
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include <console/console.h> #include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>

1
src/northbridge/intel/sandybridge/early_init.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/acpi.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <elog.h> #include <elog.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>

1
src/soc/amd/common/block/pi/heapmanager.c
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@ -13,7 +13,6 @@
#include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper.h>
#include <arch/acpi.h>
#include <amdblocks/BiosCallOuts.h> #include <amdblocks/BiosCallOuts.h>
#include <cbmem.h> #include <cbmem.h>
#include <string.h> #include <string.h>

1
src/soc/intel/baytrail/placeholders.c
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@ -12,7 +12,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <device/pci_rom.h> #include <device/pci_rom.h>
#include <soc/acpi.h> #include <soc/acpi.h>

1
src/soc/intel/braswell/placeholders.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <device/pci_rom.h> #include <device/pci_rom.h>
#include <soc/acpi.h> #include <soc/acpi.h>

1
src/soc/intel/braswell/xhci.c
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@ -15,7 +15,6 @@
* *
*/ */
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>

1
src/soc/intel/broadwell/cpu.c
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@ -18,7 +18,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <string.h> #include <string.h>
#include <arch/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>

1
src/soc/intel/denverton_ns/systemagent.c
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@ -16,7 +16,6 @@
*/ */
#include <console/console.h> #include <console/console.h>
#include <arch/acpi.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <stdint.h> #include <stdint.h>

1
src/soc/intel/fsp_broadwell_de/ramstage.c
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@ -16,7 +16,6 @@
#include <stdlib.h> #include <stdlib.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>

1
src/southbridge/amd/agesa/hudson/early_setup.c
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@ -19,7 +19,6 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <reset.h> #include <reset.h>
#include "hudson.h" #include "hudson.h"

3
src/southbridge/amd/agesa/hudson/hudson.c
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@ -14,10 +14,7 @@
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <arch/acpi.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h> #include <device/pci_def.h>

1
src/southbridge/amd/pi/hudson/early_setup.c
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@ -21,7 +21,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <reset.h> #include <reset.h>
#include "hudson.h" #include "hudson.h"