diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 9eb60c74c9..41d683b18a 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -168,15 +168,14 @@ void dram_xover(ramctr_timing *ctrl)
 
 static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
 {
-	u32 addr, cpu, stretch;
+	u32 addr, stretch;
 
 	stretch = ctrl->ref_card_offset[channel];
 	/*
 	 * ODT stretch:
 	 * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel.
 	 */
-	cpu = cpu_get_cpuid();
-	if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
+	if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) {
 		if (stretch == 2)
 			stretch = 3;
 
@@ -2992,10 +2991,8 @@ void set_scrambling_seed(ramctr_timing *ctrl)
 	}
 }
 
-void set_wmm_behavior(void)
+void set_wmm_behavior(const u32 cpu)
 {
-	u32 cpu = cpu_get_cpuid();
-
 	if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
 		MCHBAR32(SC_WDBWM) = 0x141d1519;
 	} else {
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 0cbac8ae20..0ff9265052 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -181,7 +181,7 @@ void normalize_training(ramctr_timing *ctrl);
 void write_controller_mr(ramctr_timing *ctrl);
 int channel_test(ramctr_timing *ctrl);
 void set_scrambling_seed(ramctr_timing *ctrl);
-void set_wmm_behavior(void);
+void set_wmm_behavior(const u32 cpu);
 void prepare_training(ramctr_timing *ctrl);
 void set_read_write_timings(ramctr_timing *ctrl);
 void set_normal_operation(ramctr_timing *ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 06d23825b6..a714e535b4 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -609,7 +609,7 @@ int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in
 	MCHBAR32(SCHED_CBIT) = 0x10100005;
 
 	/* Set up watermarks and starvation counter */
-	set_wmm_behavior();
+	set_wmm_behavior(ctrl->cpu);
 
 	/* Clear IO reset bit */
 	MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);
diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c
index c554c3aa89..a823d50398 100644
--- a/src/northbridge/intel/sandybridge/raminit_sandy.c
+++ b/src/northbridge/intel/sandybridge/raminit_sandy.c
@@ -433,7 +433,7 @@ int try_init_dram_ddr3_snb(ramctr_timing *ctrl, int fast_boot, int s3_resume, in
 	MCHBAR32(SCHED_CBIT) = 0x10100005;
 
 	/* Set up watermarks and starvation counter */
-	set_wmm_behavior();
+	set_wmm_behavior(ctrl->cpu);
 
 	/* Clear IO reset bit */
 	MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5);