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mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16 

This bit is used to indicate xHCI routing across reboots. If anything,
coreboot should act on it, not set it during boot. ASL code would be
supposed to set it.

Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-17 00:58:15 +01:00 committed by Patrick Georgi
parent ce20697513
commit 89b8c23830
11 changed files with 0 additions and 69 deletions
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5
src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
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@ -26,11 +26,6 @@
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void bootblock_mainboard_early_init(void)
{
/* Initialize SuperIO */

2
src/mainboard/lenovo/s230u/early_init.c
View File

@ -29,8 +29,6 @@
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
/* Memory map KB9012 EC registers */
pci_write_config32(
PCH_LPC_DEV, LGMR,

5
src/mainboard/lenovo/t420/early_init.c
View File

@ -49,11 +49,6 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0: system port 4, OC0 */

5
src/mainboard/lenovo/t420s/early_init.c
View File

@ -49,11 +49,6 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 0, 1, -1 }, /* P0 empty */
{ 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */

2
src/mainboard/lenovo/t430s/Makefile.inc
View File

@ -20,5 +20,3 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd
bootblock-y += early_init.c
romstage-y += early_init.c

25
src/mainboard/lenovo/t430s/early_init.c
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@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

5
src/mainboard/lenovo/t520/early_init.c
View File

@ -51,11 +51,6 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
{ 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */

5
src/mainboard/lenovo/t530/early_init.c
View File

@ -51,11 +51,6 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();

5
src/mainboard/lenovo/x1_carbon_gen1/early_init.c
View File

@ -28,11 +28,6 @@
#include <southbridge/intel/common/gpio.h>
#include <cbfs.h>
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled, current, OC pin */
{ 0, 3, 0 }, /* P00 disconnected */

5
src/mainboard/lenovo/x220/early_init.c
View File

@ -27,11 +27,6 @@
#include <southbridge/intel/common/gpio.h>
#include <cpu/x86/msr.h>
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {

5
src/mainboard/lenovo/x230/early_init.c
View File

@ -24,11 +24,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
void mainboard_pch_lpc_setup(void)
{
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
{ 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */