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Fix the indent and whitespace to match LinuxBIOS standards 

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jordan Crouse 2007-05-10 18:00:24 +00:00 committed by Stefan Reinauer
parent 4fcb3ba93f
commit 89d7cd2c83
5 changed files with 166 additions and 133 deletions
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14
src/mainboard/amd/norwich/auto.c
View File

@ -42,11 +42,11 @@
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xA0 #define DIMM0 0xA0
#define DIMM1 0xA2 #define DIMM1 0xA2
@ -60,7 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void msr_init(void) static void msr_init(void)
{ {
/* Setup access to the MC for low memory. Note MC not setup yet. */ /* Setup access to the MC for low memory. Note MC not setup yet. */
__builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02); __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
__builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000); __builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000);
__builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000); __builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000);
@ -76,8 +76,8 @@ static void mb_gpio_init(void)
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
static const struct mem_controller memctrl [] = { static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
}; };
SystemPreInit(); SystemPreInit();
@ -89,8 +89,8 @@ static void main(unsigned long bist)
* it is counting on some early MSR setup * it is counting on some early MSR setup
* for cs5536 * for cs5536
*/ */
/* cs5536_disable_internal_uart disable them for now, set them up later...*/ /* cs5536_disable_internal_uart disable them for now, set them up later... */
cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
mb_gpio_init(); mb_gpio_init();
uart_init(); uart_init();
console_init(); console_init();

24
src/mainboard/amd/norwich/cache_as_ram_auto.c
View File

@ -42,11 +42,11 @@
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define ManualConf 0 /* Do automatic strapped PLL config */ #define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030 #define PLLMSRlo 0x02000030
#define DIMM0 0xA0 #define DIMM0 0xA0
#define DIMM1 0xA2 #define DIMM1 0xA2
@ -62,11 +62,11 @@ static void msr_init(void)
msr_t msr; msr_t msr;
/* Setup access to the cache for under 1MB. */ /* Setup access to the cache for under 1MB. */
msr.hi = 0x24fffc02; msr.hi = 0x24fffc02;
msr.lo = 0x1000A000; /* 0-A0000 write back */ msr.lo = 0x1000A000; /* 0-A0000 write back */
wrmsr(CPU_RCONF_DEFAULT, msr); wrmsr(CPU_RCONF_DEFAULT, msr);
msr.hi = 0x0; /* write back */ msr.hi = 0x0; /* write back */
msr.lo = 0x0; msr.lo = 0x0;
wrmsr(CPU_RCONF_A0_BF, msr); wrmsr(CPU_RCONF_A0_BF, msr);
wrmsr(CPU_RCONF_C0_DF, msr); wrmsr(CPU_RCONF_C0_DF, msr);
wrmsr(CPU_RCONF_E0_FF, msr); wrmsr(CPU_RCONF_E0_FF, msr);
@ -81,11 +81,11 @@ static void msr_init(void)
wrmsr(MSR_GLIU0 + 0x21, msr); wrmsr(MSR_GLIU0 + 0x21, msr);
msr.hi = 0x20000000; msr.hi = 0x20000000;
msr.lo = 0xfff80; msr.lo = 0xfff80;
wrmsr(MSR_GLIU1 + 0x20, msr); wrmsr(MSR_GLIU1 + 0x20, msr);
msr.hi = 0x20000000; msr.hi = 0x20000000;
msr.lo = 0x80fffe0; msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU1 + 0x21, msr); wrmsr(MSR_GLIU1 + 0x21, msr);
} }
@ -99,8 +99,8 @@ void cache_as_ram_main(void)
{ {
POST_CODE(0x01); POST_CODE(0x01);
static const struct mem_controller memctrl [] = { static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
}; };
SystemPreInit(); SystemPreInit();
@ -112,8 +112,8 @@ void cache_as_ram_main(void)
* it is counting on some early MSR setup * it is counting on some early MSR setup
* for cs5536 * for cs5536
*/ */
/* cs5536_disable_internal_uart disable them for now, set them up later...*/ /* cs5536_disable_internal_uart disable them for now, set them up later... */
cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */ cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
mb_gpio_init(); mb_gpio_init();
uart_init(); uart_init();
console_init(); console_init();
@ -125,7 +125,7 @@ void cache_as_ram_main(void)
sdram_initialize(1, memctrl); sdram_initialize(1, memctrl);
/* Check all of memory */ /* Check all of memory */
/*ram_check(0x00000000, 640*1024);*/ /*ram_check(0x00000000, 640*1024); */
/* Memory is setup. Return to cache_as_ram.inc and continue to boot */ /* Memory is setup. Return to cache_as_ram.inc and continue to boot */
return; return;

27
src/mainboard/amd/norwich/failover.c
View File

@ -12,23 +12,20 @@ static unsigned long main(unsigned long bist)
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
if (do_normal_boot()) { if (do_normal_boot()) {
goto normal_image; goto normal_image;
} } else {
else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
asm volatile ("jmp __normal_image" asm volatile ("jmp __normal_image": /* outputs */
: /* outputs */ :"a" (bist) /* inputs */
: "a" (bist) /* inputs */ : /* clobbers */
: /* clobbers */ );
); cpu_reset:
cpu_reset: asm volatile ("jmp __cpu_reset": /* outputs */
asm volatile ("jmp __cpu_reset" :"a" (bist) /* inputs */
: /* outputs */ : /* clobbers */
: "a"(bist) /* inputs */ );
: /* clobbers */ fallback_image:
);
fallback_image:
#endif #endif
return bist; return bist;
} }

72
src/mainboard/amd/norwich/irq_tables.c
View File

@ -30,43 +30,43 @@
#define PIRQD 10 #define PIRQD 10
/* Map */ /* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */ /* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
0x00, /* IRQs devoted exclusively to PCI usage */ 0x00, /* IRQs devoted exclusively to PCI usage */
0x100B, /* Vendor */ 0x100B, /* Vendor */
0x002B, /* Device */ 0x002B, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ {
/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
{0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00,(0x0D<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
{0x00,(0x0E<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */ {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
{0x00,(0x0B<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */ {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
{0x00,(0x0C<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */ {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
} }
}; };
unsigned long write_pirq_routing_table(unsigned long addr)
unsigned long write_pirq_routing_table(unsigned long addr){ {
int i, j, k, num_entries; int i, j, k, num_entries;
unsigned char pirq[4]; unsigned char pirq[4];
uint16_t chipset_irq_map; uint16_t chipset_irq_map;
@ -78,24 +78,26 @@ unsigned long write_pirq_routing_table(unsigned long addr){
/* Set up chipset IRQ steering */ /* Set up chipset IRQ steering */
pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map); printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
chipset_irq_map);
outl(pciAddr & ~3, 0xCF8); outl(pciAddr & ~3, 0xCF8);
outl(chipset_irq_map, 0xCFC); outl(chipset_irq_map, 0xCFC);
pirq_tbl = (struct irq_routing_table *)(addr); pirq_tbl = (struct irq_routing_table *)(addr);
num_entries = (pirq_tbl->size - 32)/16; num_entries = (pirq_tbl->size - 32) / 16;
/* Set PCI IRQs */ /* Set PCI IRQs */
for (i=0; i < num_entries; i++){ for (i = 0; i < num_entries; i++) {
printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
for (j = 0; j < 4; j++){ pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap); for (j = 0; j < 4; j++) {
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */ printk_debug("INT: %c bitmap: %x ", 'A' + j,
pirq_tbl->slots[i].irq[j].bitmap);
for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* finds lsb in bitmap to IRQ# */
pirq[j] = k; pirq[j] = k;
printk_debug("PIRQ: %d\n", k); printk_debug("PIRQ: %d\n", k);
} }
pci_assign_irqs(pirq_tbl->slots[i].bus, pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
} }
/* put the PIR table in memory and checksum */ /* put the PIR table in memory and checksum */

162
src/mainboard/amd/norwich/mainboard.c
View File

@ -27,143 +27,177 @@
#include "chip.h" #include "chip.h"
/* Print the platform configuration - do before PCI init or it will not work right */ /* Print the platform configuration - do before PCI init or it will not work right */
void print_conf(void) { void print_conf(void)
{
#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
int i; int i;
unsigned long iol; unsigned long iol;
msr_t msr; msr_t msr;
int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
CPU_DM_CONFIG0, CPU_RCONF_DEFAULT, CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF,
CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END CPU_RCONF_E0_FF,
}; CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
};
int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, int gliu0_msr_defs[] =
GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4,
GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
GLIU0_GLD_MSR_COH, GL_END MSR_GLIU0_SHADOW,
}; GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3,
GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
GLIU0_GLD_MSR_COH, GL_END
};
int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6, int gliu1_msr_defs[] =
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3,
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9,
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, MSR_GLIU1_BASE10,
GLIU1_GLD_MSR_COH, GL_END GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3,
}; MSR_GLIU1_SHADOW,
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
GLIU1_GLD_MSR_COH, GL_END
};
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4, int rconf_msr[] =
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
}; CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
};
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT, int cs5536_msr[] =
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO,
}; MDD_PIN_OPT,
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
};
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF, int pci_msr[] =
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF,
GL_END GLPCI_E0_FF,
}; GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR,
GLPCI_SPARE,
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4, GL_END
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8, };
MDD_DMA_SHAD9, GL_END
};
int dma_msr[] =
{ MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3,
MDD_DMA_SHAD4,
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
MDD_DMA_SHAD9, GL_END
};
printk_debug("---------- CPU ------------\n"); printk_debug("---------- CPU ------------\n");
for(i = 0; cpu_msr_defs[i] != GL_END; i++) { for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
msr = rdmsr(cpu_msr_defs[i]); msr = rdmsr(cpu_msr_defs[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
cpu_msr_defs[i], msr.hi, msr.lo);
} }
printk_debug("---------- GLIU 0 ------------\n"); printk_debug("---------- GLIU 0 ------------\n");
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) { for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu0_msr_defs[i]); msr = rdmsr(gliu0_msr_defs[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu0_msr_defs[i], msr.hi, msr.lo);
} }
printk_debug("---------- GLIU 1 ------------\n"); printk_debug("---------- GLIU 1 ------------\n");
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) { for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu1_msr_defs[i]); msr = rdmsr(gliu1_msr_defs[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu1_msr_defs[i], msr.hi, msr.lo);
} }
printk_debug("---------- RCONF ------------\n"); printk_debug("---------- RCONF ------------\n");
for(i = 0; rconf_msr[i] != GL_END; i++) { for (i = 0; rconf_msr[i] != GL_END; i++) {
msr = rdmsr(rconf_msr[i]); msr = rdmsr(rconf_msr[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
msr.hi, msr.lo);
} }
printk_debug("---------- VARIA ------------\n"); printk_debug("---------- VARIA ------------\n");
msr = rdmsr(0x51300010); msr = rdmsr(0x51300010);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
msr.lo);
msr = rdmsr(0x51400015); msr = rdmsr(0x51400015);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
msr.lo);
printk_debug("---------- DIVIL IRQ ------------\n"); printk_debug("---------- DIVIL IRQ ------------\n");
msr = rdmsr(MDD_IRQM_YLOW); msr = rdmsr(MDD_IRQM_YLOW);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
msr.lo);
msr = rdmsr(MDD_IRQM_YHIGH); msr = rdmsr(MDD_IRQM_YHIGH);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
msr.hi, msr.lo);
msr = rdmsr(MDD_IRQM_ZLOW); msr = rdmsr(MDD_IRQM_ZLOW);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
msr.lo);
msr = rdmsr(MDD_IRQM_ZHIGH); msr = rdmsr(MDD_IRQM_ZHIGH);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
msr.hi, msr.lo);
printk_debug("---------- PCI ------------\n"); printk_debug("---------- PCI ------------\n");
for(i = 0; pci_msr[i] != GL_END; i++) { for (i = 0; pci_msr[i] != GL_END; i++) {
msr = rdmsr(pci_msr[i]); msr = rdmsr(pci_msr[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
msr.hi, msr.lo);
} }
printk_debug("---------- LPC/UART DMA ------------\n"); printk_debug("---------- LPC/UART DMA ------------\n");
for(i = 0; dma_msr[i] != GL_END; i++) { for (i = 0; dma_msr[i] != GL_END; i++) {
msr = rdmsr(dma_msr[i]); msr = rdmsr(dma_msr[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
msr.hi, msr.lo);
} }
printk_debug("---------- CS5536 ------------\n"); printk_debug("---------- CS5536 ------------\n");
for(i = 0; cs5536_msr[i] != GL_END; i++) { for (i = 0; cs5536_msr[i] != GL_END; i++) {
msr = rdmsr(cs5536_msr[i]); msr = rdmsr(cs5536_msr[i]);
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo); printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
msr.hi, msr.lo);
} }
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); printk_debug("IOR 0x%08X is now 0x%08X\n",
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
iol = inl(GPIOL_EVENTS_ENABLE); iol = inl(GPIOL_EVENTS_ENABLE);
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); printk_debug("IOR 0x%08X is now 0x%08X\n",
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
iol = inl(GPIOL_INPUT_INVERT_ENABLE); iol = inl(GPIOL_INPUT_INVERT_ENABLE);
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); printk_debug("IOR 0x%08X is now 0x%08X\n",
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
iol = inl(GPIO_MAPPER_X); iol = inl(GPIO_MAPPER_X);
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR iol);
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
} }
static void init(struct device *dev) { static void init(struct device *dev)
{
printk_debug("Norwich ENTER %s\n", __FUNCTION__); printk_debug("Norwich ENTER %s\n", __FUNCTION__);
printk_debug("Norwich EXIT %s\n", __FUNCTION__); printk_debug("Norwich EXIT %s\n", __FUNCTION__);
} }
static void enable_dev(struct device *dev) static void enable_dev(struct device *dev)
{ {
dev->ops->init = init; dev->ops->init = init;
} }
struct chip_operations mainboard_amd_norwich_ops = { struct chip_operations mainboard_amd_norwich_ops = {
CHIP_NAME("AMD Norwich Mainboard") CHIP_NAME("AMD Norwich Mainboard")
.enable_dev = enable_dev, .enable_dev = enable_dev,
}; };