Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jordan Crouse
Stefan Reinauer
parent
4fcb3ba93f
commit
89d7cd2c83
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@ -42,11 +42,11 @@
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRlo 0x02000030
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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@ -60,7 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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static void msr_init(void)
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{
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/* Setup access to the MC for low memory. Note MC not setup yet. */
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__builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
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__builtin_wrmsr(CPU_RCONF_DEFAULT, 0x10f3bf00, 0x24fffc02);
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__builtin_wrmsr(MSR_GLIU0 + 0x20, 0xfff80, 0x20000000);
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__builtin_wrmsr(MSR_GLIU0 + 0x21, 0x80fffe0, 0x20000000);
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@ -76,8 +76,8 @@ static void mb_gpio_init(void)
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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static const struct mem_controller memctrl[] = {
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{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
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};
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SystemPreInit();
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@ -89,8 +89,8 @@ static void main(unsigned long bist)
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* it is counting on some early MSR setup
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* for cs5536
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*/
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/* cs5536_disable_internal_uart disable them for now, set them up later...*/
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cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
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/* cs5536_disable_internal_uart disable them for now, set them up later... */
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cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
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mb_gpio_init();
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uart_init();
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console_init();
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@ -42,11 +42,11 @@
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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}
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#define ManualConf 0 /* Do automatic strapped PLL config */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
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#define PLLMSRlo 0x02000030
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#define DIMM0 0xA0
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#define DIMM1 0xA2
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@ -62,11 +62,11 @@ static void msr_init(void)
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msr_t msr;
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/* Setup access to the cache for under 1MB. */
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msr.hi = 0x24fffc02;
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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wrmsr(CPU_RCONF_DEFAULT, msr);
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msr.hi = 0x0; /* write back */
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msr.lo = 0x0;
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msr.hi = 0x0; /* write back */
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msr.lo = 0x0;
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wrmsr(CPU_RCONF_A0_BF, msr);
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wrmsr(CPU_RCONF_C0_DF, msr);
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wrmsr(CPU_RCONF_E0_FF, msr);
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@ -81,11 +81,11 @@ static void msr_init(void)
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wrmsr(MSR_GLIU0 + 0x21, msr);
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msr.hi = 0x20000000;
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msr.lo = 0xfff80;
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msr.lo = 0xfff80;
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wrmsr(MSR_GLIU1 + 0x20, msr);
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msr.hi = 0x20000000;
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msr.lo = 0x80fffe0;
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msr.lo = 0x80fffe0;
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wrmsr(MSR_GLIU1 + 0x21, msr);
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}
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@ -99,8 +99,8 @@ void cache_as_ram_main(void)
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{
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POST_CODE(0x01);
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static const struct mem_controller memctrl [] = {
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{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
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static const struct mem_controller memctrl[] = {
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{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
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};
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SystemPreInit();
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@ -112,8 +112,8 @@ void cache_as_ram_main(void)
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* it is counting on some early MSR setup
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* for cs5536
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*/
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/* cs5536_disable_internal_uart disable them for now, set them up later...*/
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cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
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/* cs5536_disable_internal_uart disable them for now, set them up later... */
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cs5536_setup_onchipuart(); /* if debug. real setup done in chipset init via config.lb */
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mb_gpio_init();
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uart_init();
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console_init();
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@ -125,7 +125,7 @@ void cache_as_ram_main(void)
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sdram_initialize(1, memctrl);
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/* Check all of memory */
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/*ram_check(0x00000000, 640*1024);*/
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/*ram_check(0x00000000, 640*1024); */
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/* Memory is setup. Return to cache_as_ram.inc and continue to boot */
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return;
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@ -12,23 +12,20 @@ static unsigned long main(unsigned long bist)
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/* This is the primary cpu how should I boot? */
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if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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} else {
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goto fallback_image;
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}
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normal_image:
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asm volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist) /* inputs */
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: /* clobbers */
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);
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cpu_reset:
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asm volatile ("jmp __cpu_reset"
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: /* outputs */
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: "a"(bist) /* inputs */
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: /* clobbers */
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);
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fallback_image:
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normal_image:
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asm volatile ("jmp __normal_image": /* outputs */
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:"a" (bist) /* inputs */
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: /* clobbers */
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);
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cpu_reset:
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asm volatile ("jmp __cpu_reset": /* outputs */
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:"a" (bist) /* inputs */
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: /* clobbers */
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);
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fallback_image:
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#endif
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return bist;
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}
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@ -30,43 +30,43 @@
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#define PIRQD 10
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/* Map */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
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#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
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#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
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#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
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/* Link */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
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#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
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#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
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#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x0F<<3)|0x0, /* Where the interrupt router lies (dev) */
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(0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0x00, /* IRQs devoted exclusively to PCI usage */
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0x100B, /* Vendor */
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0x002B, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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0, /* Crap (miniport) */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00,(0x01<<3)|0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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{0x00,(0x0F<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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{0x00,(0x0D<<3)|0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
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{0x00,(0x0E<<3)|0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
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{0x00,(0x0B<<3)|0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
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{0x00,(0x0C<<3)|0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
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}
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/* If you change the number of entries, change the IRQ_SLOT_COUNT above! */
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/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
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{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
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{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */
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{0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x2, 0x0}, /* slot2 */
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{0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x3, 0x0}, /* slot3 */
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{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0}, /* slot4 */
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr){
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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int i, j, k, num_entries;
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unsigned char pirq[4];
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uint16_t chipset_irq_map;
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@ -78,24 +78,26 @@ unsigned long write_pirq_routing_table(unsigned long addr){
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/* Set up chipset IRQ steering */
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pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
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printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
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chipset_irq_map);
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outl(pciAddr & ~3, 0xCF8);
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outl(chipset_irq_map, 0xCFC);
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pirq_tbl = (struct irq_routing_table *)(addr);
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num_entries = (pirq_tbl->size - 32)/16;
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num_entries = (pirq_tbl->size - 32) / 16;
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/* Set PCI IRQs */
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for (i=0; i < num_entries; i++){
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++){
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printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
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for (i = 0; i < num_entries; i++) {
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printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
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pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++) {
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printk_debug("INT: %c bitmap: %x ", 'A' + j,
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pirq_tbl->slots[i].irq[j].bitmap);
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for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* finds lsb in bitmap to IRQ# */
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pirq[j] = k;
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printk_debug("PIRQ: %d\n", k);
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}
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pci_assign_irqs(pirq_tbl->slots[i].bus,
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pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
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pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn >> 3, pirq); /* bus, device, slots IRQs for {A,B,C,D} */
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}
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/* put the PIR table in memory and checksum */
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@ -27,143 +27,177 @@
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#include "chip.h"
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/* Print the platform configuration - do before PCI init or it will not work right */
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void print_conf(void) {
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void print_conf(void)
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{
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#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
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int i;
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unsigned long iol;
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msr_t msr;
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
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CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
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CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF, CPU_RCONF_E0_FF,
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CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
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};
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int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG,
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CPU_DM_CONFIG0, CPU_RCONF_DEFAULT,
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CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, CPU_RCONF_C0_DF,
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CPU_RCONF_E0_FF,
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CPU_RCONF_SMM, CPU_RCONF_DMM, GLCP_DELAY_CONTROLS, GL_END
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};
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int gliu0_msr_defs[] = {MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
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GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, MSR_GLIU0_SHADOW,
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GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
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GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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GLIU0_GLD_MSR_COH, GL_END
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};
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int gliu0_msr_defs[] =
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{ MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, MSR_GLIU0_BASE4,
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MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
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GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
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GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
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MSR_GLIU0_SHADOW,
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GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, GLIU0_IOD_BM_2,
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GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, GLIU0_IOD_SC_3,
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GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
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GLIU0_GLD_MSR_COH, GL_END
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};
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int gliu1_msr_defs[] = {MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
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MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9, MSR_GLIU1_BASE10,
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GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
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GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
int gliu1_msr_defs[] =
|
||||
{ MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, MSR_GLIU1_BASE3,
|
||||
MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, MSR_GLIU1_BASE6,
|
||||
MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, MSR_GLIU1_BASE9,
|
||||
MSR_GLIU1_BASE10,
|
||||
GLIU1_P2D_R_0, GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3,
|
||||
MSR_GLIU1_SHADOW,
|
||||
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2,
|
||||
GLIU1_IOD_SC_0, GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
|
||||
GLIU1_GLD_MSR_COH, GL_END
|
||||
};
|
||||
|
||||
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
int rconf_msr[] =
|
||||
{ CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, CPU_RCONF4,
|
||||
CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
|
||||
};
|
||||
|
||||
int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO, MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
int cs5536_msr[] =
|
||||
{ MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LEG_IO,
|
||||
MDD_PIN_OPT,
|
||||
MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, MDD_IRQM_PRIM, GL_END
|
||||
};
|
||||
|
||||
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF, GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3, MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
int pci_msr[] =
|
||||
{ GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, GLPCI_C0_DF,
|
||||
GLPCI_E0_FF,
|
||||
GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, GLPCI_RC3, GLPCI_ExtMSR,
|
||||
GLPCI_SPARE,
|
||||
GL_END
|
||||
};
|
||||
|
||||
int dma_msr[] =
|
||||
{ MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, MDD_DMA_SHAD3,
|
||||
MDD_DMA_SHAD4,
|
||||
MDD_DMA_SHAD5, MDD_DMA_SHAD6, MDD_DMA_SHAD7, MDD_DMA_SHAD8,
|
||||
MDD_DMA_SHAD9, GL_END
|
||||
};
|
||||
|
||||
printk_debug("---------- CPU ------------\n");
|
||||
|
||||
for(i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(cpu_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
cpu_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 0 ------------\n");
|
||||
|
||||
for(i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu0_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
gliu0_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- GLIU 1 ------------\n");
|
||||
|
||||
for(i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
|
||||
msr = rdmsr(gliu1_msr_defs[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
|
||||
gliu1_msr_defs[i], msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- RCONF ------------\n");
|
||||
|
||||
for(i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
for (i = 0; rconf_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(rconf_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- VARIA ------------\n");
|
||||
msr = rdmsr(0x51300010);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
|
||||
msr.lo);
|
||||
|
||||
msr = rdmsr(0x51400015);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
|
||||
msr.lo);
|
||||
|
||||
printk_debug("---------- DIVIL IRQ ------------\n");
|
||||
msr = rdmsr(MDD_IRQM_YLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
|
||||
msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_YHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
|
||||
msr.hi, msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZLOW);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
|
||||
msr.lo);
|
||||
msr = rdmsr(MDD_IRQM_ZHIGH);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, msr.hi, msr.lo);
|
||||
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
|
||||
msr.hi, msr.lo);
|
||||
|
||||
printk_debug("---------- PCI ------------\n");
|
||||
|
||||
for(i = 0; pci_msr[i] != GL_END; i++) {
|
||||
for (i = 0; pci_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(pci_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- LPC/UART DMA ------------\n");
|
||||
|
||||
for(i = 0; dma_msr[i] != GL_END; i++) {
|
||||
for (i = 0; dma_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(dma_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
printk_debug("---------- CS5536 ------------\n");
|
||||
|
||||
for(i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
for (i = 0; cs5536_msr[i] != GL_END; i++) {
|
||||
msr = rdmsr(cs5536_msr[i]);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], msr.hi, msr.lo);
|
||||
printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
|
||||
msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
|
||||
iol = inl(GPIOL_EVENTS_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
|
||||
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n",
|
||||
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
|
||||
iol = inl(GPIO_MAPPER_X);
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
|
||||
iol);
|
||||
#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
|
||||
}
|
||||
|
||||
static void init(struct device *dev) {
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
printk_debug("Norwich ENTER %s\n", __FUNCTION__);
|
||||
printk_debug("Norwich EXIT %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
dev->ops->init = init;
|
||||
dev->ops->init = init;
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_amd_norwich_ops = {
|
||||
CHIP_NAME("AMD Norwich Mainboard")
|
||||
.enable_dev = enable_dev,
|
||||
.enable_dev = enable_dev,
|
||||
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue