From 89f5292ee63cb6f387c06bfbdb4343cc675bc938 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 19 Mar 2014 11:48:33 -0500 Subject: [PATCH] baytrail: move cache-as-ram base address to 0xfe000000 Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson Reviewed-by: Duncan Laurie (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 3669c30f54..bc90b11d73 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -113,7 +113,7 @@ endif # HAVE_MRC config DCACHE_RAM_BASE hex - default 0xff800000 + default 0xfe000000 config DCACHE_RAM_SIZE hex