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skylake/devicetree: Add LPC EC decode range 

Define LPC decode ranges for EC communication.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu to ensure no EC timeout error

Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15898
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2016-07-26 15:37:11 +05:30 committed by Andrey Petrov
parent 50b9258a0b
commit 89f6d6079e
4 changed files with 8 additions and 4 deletions
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3
src/mainboard/google/chell/devicetree.cb
View File

@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command range is in 0x800-0x8ff
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"

3
src/mainboard/google/glados/devicetree.cb
View File

@ -13,8 +13,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command range is in 0x800-0x8ff
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"

3
src/mainboard/google/lars/devicetree.cb
View File

@ -12,8 +12,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command range is in 0x800-0x8ff
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"

3
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -12,8 +12,9 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
# EC host command range is in 0x800-0x8ff
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"