haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2618 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin
Ronald G. Minnich
parent
b9ea8b3fb0
commit
89f79a019f
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@ -21,24 +21,23 @@
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <stdlib.h>
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#include "pcie_config.c"
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#include "haswell.h"
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#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
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#define PCI_DEV_HSW PCI_DEV(0, 0, 0)
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void intel_northbridge_haswell_finalize_smm(void)
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{
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pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */
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pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */
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pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */
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pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */
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pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */
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pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */
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pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */
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pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */
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pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */
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pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */
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pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */
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pci_or_config16(PCI_DEV_HSW, 0x50, 1 << 0); /* GGC */
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pci_or_config32(PCI_DEV_HSW, 0x5c, 1 << 0); /* DPR */
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pci_or_config32(PCI_DEV_HSW, 0x78, 1 << 10); /* ME */
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pci_or_config32(PCI_DEV_HSW, 0x90, 1 << 0); /* REMAPBASE */
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pci_or_config32(PCI_DEV_HSW, 0x98, 1 << 0); /* REMAPLIMIT */
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pci_or_config32(PCI_DEV_HSW, 0xa0, 1 << 0); /* TOM */
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pci_or_config32(PCI_DEV_HSW, 0xa8, 1 << 0); /* TOUUD */
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pci_or_config32(PCI_DEV_HSW, 0xb0, 1 << 0); /* BDSM */
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pci_or_config32(PCI_DEV_HSW, 0xb4, 1 << 0); /* BGSM */
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pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */
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pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */
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MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */
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MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */
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@ -1,89 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "haswell.h"
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static inline __attribute__ ((always_inline))
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u8 pcie_read_config8(device_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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return read8(addr);
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}
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static inline __attribute__ ((always_inline))
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u16 pcie_read_config16(device_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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return read16(addr);
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}
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static inline __attribute__ ((always_inline))
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u32 pcie_read_config32(device_t dev, unsigned int where)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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return read32(addr);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config8(device_t dev, unsigned int where, u8 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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write8(addr, value);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config16(device_t dev, unsigned int where, u16 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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write16(addr, value);
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}
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static inline __attribute__ ((always_inline))
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void pcie_write_config32(device_t dev, unsigned int where, u32 value)
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{
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unsigned long addr;
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addr = DEFAULT_PCIEXBAR | dev | where;
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write32(addr, value);
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}
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static inline __attribute__ ((always_inline))
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void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
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{
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u8 value = pcie_read_config8(dev, where);
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pcie_write_config8(dev, where, value | ormask);
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}
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static inline __attribute__ ((always_inline))
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void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
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{
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u16 value = pcie_read_config16(dev, where);
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pcie_write_config16(dev, where, value | ormask);
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}
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static inline __attribute__ ((always_inline))
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void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
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{
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u32 value = pcie_read_config32(dev, where);
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pcie_write_config32(dev, where, value | ormask);
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}
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@ -21,7 +21,6 @@
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <console/post_codes.h>
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#include <northbridge/intel/haswell/pcie_config.c>
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#include <spi-generic.h>
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#include "pch.h"
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@ -51,15 +50,15 @@ void intel_pch_finalize_smm(void)
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RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
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/* Global SMI Lock */
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pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
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pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
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/* GEN_PMCON Lock */
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pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
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pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
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/* R/WO registers */
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RCBA32(0x21a4) = RCBA32(0x21a4);
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pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
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pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
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pci_write_config32(PCI_DEV(0, 27, 0), 0x74,
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pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
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/* Indicate finalize step with post code */
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outb(POST_OS_BOOT, 0x80);
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@ -39,7 +39,6 @@
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#ifdef __SMM__
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# include <arch/romcc_io.h>
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# include <northbridge/intel/haswell/pcie_config.c>
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#else
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# include <device/device.h>
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# include <device/pci.h>
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@ -496,14 +495,14 @@ void intel_me_finalize_smm(void)
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u32 reg32;
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mei_base_address =
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pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
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pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
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/* S3 path will have hidden this device already */
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if (!mei_base_address || mei_base_address == 0xfffffff0)
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return;
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/* Make sure ME is in a mode that expects EOP */
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reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
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reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
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memcpy(&hfs, ®32, sizeof(u32));
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/* Abort and leave device alone if not normal mode */
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@ -516,10 +515,10 @@ void intel_me_finalize_smm(void)
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mkhi_end_of_post();
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/* Make sure IO is disabled */
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reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
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reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND);
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reg32 &= ~(PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
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pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
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/* Hide the PCI device */
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RCBA32_OR(FD2, PCH_DISABLE_MEI1);
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@ -38,7 +38,6 @@
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include <northbridge/intel/haswell/haswell.h>
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#include <northbridge/intel/haswell/pcie_config.c>
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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@ -65,7 +64,7 @@ static u32 tseg_base = 0;
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u32 smi_get_tseg_base(void)
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{
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if (!tseg_base)
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tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
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tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
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return tseg_base;
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}
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void tseg_relocate(void **ptr)
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@ -302,7 +301,7 @@ static void southbridge_gate_memory_reset(void)
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u32 reg32;
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u16 gpiobase;
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gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
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gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
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if (!gpiobase)
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return;
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@ -388,13 +387,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
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/* Always set the flag in case CMOS was changed on runtime. For
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* "KEEP", switch to "OFF" - KEEP is software emulated
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*/
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reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
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if (s5pwr == MAINBOARD_POWER_ON) {
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reg8 &= ~1;
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} else {
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reg8 |= 1;
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}
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pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
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/* also iterates over all bridges on bus 0 */
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busmaster_disable_on_bus(0);
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@ -625,7 +624,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
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if (tco_sts & (1 << 8)) { // BIOSWR
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u8 bios_cntl;
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bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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if (bios_cntl & 1) {
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/* BWE is RW, so the SMI was caused by a
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@ -639,7 +638,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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} /* No else for now? */
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} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
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/* Handle TCO timeout */
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@ -766,7 +765,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
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u32 smi_sts;
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/* Update global variable pmbase */
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pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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@ -35,19 +35,18 @@
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#ifdef __SMM__
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#include <arch/romcc_io.h>
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#include <northbridge/intel/haswell/pcie_config.c>
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#define pci_read_config_byte(dev, reg, targ)\
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*(targ) = pcie_read_config8(dev, reg)
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*(targ) = pci_read_config8(dev, reg)
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#define pci_read_config_word(dev, reg, targ)\
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*(targ) = pcie_read_config16(dev, reg)
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*(targ) = pci_read_config16(dev, reg)
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#define pci_read_config_dword(dev, reg, targ)\
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*(targ) = pcie_read_config32(dev, reg)
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*(targ) = pci_read_config32(dev, reg)
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#define pci_write_config_byte(dev, reg, val)\
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pcie_write_config8(dev, reg, val)
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pci_write_config8(dev, reg, val)
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#define pci_write_config_word(dev, reg, val)\
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pcie_write_config16(dev, reg, val)
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pci_write_config16(dev, reg, val)
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#define pci_write_config_dword(dev, reg, val)\
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pcie_write_config32(dev, reg, val)
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pci_write_config32(dev, reg, val)
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#else /* !__SMM__ */
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#include <device/device.h>
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#include <device/pci.h>
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