The parameters of memset() should be
memset(addr, value, size), right? It is an obvious bug created at r5201. I am wondering why it doesnt trouble you. I took a quick look at other files and didnt find other calling error. Trailing white spaces are also deleted. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
Zheng Bao
parent
342619526c
commit
8a0c6498a4
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@ -1,4 +1,4 @@
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/* 2005.6 by yhlu
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/* 2005.6 by yhlu
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* 2006.3 yhlu add copy data from CAR to ram
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*/
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#include "cpu/amd/car/disable_cache_as_ram.c"
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@ -55,13 +55,13 @@ static void post_cache_as_ram(void)
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unsigned testx = 0x5a5a5a5a;
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print_debug_pcar("testx = ", testx);
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/* copy data from cache as ram to
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/* copy data from cache as ram to
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ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
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*/
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#if CONFIG_RAMTOP <= 0x100000
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#error "You need to set CONFIG_RAMTOP greater than 1M"
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#endif
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/* So we can access RAM from [1M, CONFIG_RAMTOP) */
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set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
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@ -90,14 +90,14 @@ static void post_cache_as_ram(void)
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print_debug_pcar("testx = ", testx);
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print_debug("Disabling cache as ram now \r\n");
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disable_cache_as_ram_bsp();
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disable_cache_as_ram_bsp();
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print_debug("Clearing initial memory region: ");
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#if CONFIG_HAVE_ACPI_RESUME == 1
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/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
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memset((void*) CONFIG_RAMBASE, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE, 0);
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memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
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#else
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memset((void*)0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE), 0);
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memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
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#endif
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print_debug("Done\r\n");
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@ -5,7 +5,7 @@
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* 2005.02 yhlu add e0 memory hole support
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* Copyright 2005 AMD
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* 2005.08 yhlu add microcode support
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* 2005.08 yhlu add microcode support
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*/
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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@ -199,7 +199,7 @@ static void set_init_ecc_mtrrs(void)
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enable_cache();
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}
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static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
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static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
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{
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unsigned long limitk;
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unsigned long size;
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@ -226,7 +226,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
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#if 0
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/* couldn't happen, memory must on 2M boundary */
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if(limitk>endk) {
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limitk = enk;
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limitk = enk;
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}
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#endif
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size = (limitk - basek) << 10;
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@ -238,7 +238,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
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/* clear memory 2M (limitk - basek) */
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addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
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memset(addr, size, 0);
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memset(addr, 0, size);
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}
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static void init_ecc_memory(unsigned node_id)
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@ -278,7 +278,7 @@ static void init_ecc_memory(unsigned node_id)
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(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
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printk_debug("Scrubbing Disabled\n");
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}
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/* If ecc support is not enabled don't touch memory */
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dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
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@ -292,7 +292,7 @@ static void init_ecc_memory(unsigned node_id)
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#if CONFIG_HW_MEM_HOLE_SIZEK != 0
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#if CONFIG_K8_REV_F_SUPPORT == 0
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if (!is_cpu_pre_e0())
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if (!is_cpu_pre_e0())
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{
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#endif
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@ -305,7 +305,7 @@ static void init_ecc_memory(unsigned node_id)
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}
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#endif
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#endif
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/* Don't start too early */
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begink = startk;
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@ -337,10 +337,10 @@ static void init_ecc_memory(unsigned node_id)
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clear_2M_ram(basek, &mtrr_state);
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}
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}
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else
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else
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#endif
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for(basek = begink; basek < endk;
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
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basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
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{
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clear_2M_ram(basek, &mtrr_state);
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}
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@ -385,7 +385,7 @@ static inline void k8_errata(void)
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msr = rdmsr_amd(DC_CFG_MSR);
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msr.lo |= (1 << 10);
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wrmsr_amd(DC_CFG_MSR, msr);
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}
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/* I can't touch this msr on early buggy cpus */
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if (!is_cpu_pre_b3()) {
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@ -393,10 +393,10 @@ static inline void k8_errata(void)
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/* Erratum 89 ... */
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msr = rdmsr(NB_CFG_MSR);
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msr.lo |= 1 << 3;
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if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
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/* D0 later don't need it */
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/* Erratum 86 Disable data masking on C0 and
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/* Erratum 86 Disable data masking on C0 and
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* later processor revs.
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* FIXME this is only needed if ECC is enabled.
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*/
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@ -404,14 +404,14 @@ static inline void k8_errata(void)
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}
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wrmsr(NB_CFG_MSR, msr);
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}
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/* Erratum 97 ... */
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if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
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msr = rdmsr_amd(DC_CFG_MSR);
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msr.lo |= 1 << 3;
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wrmsr_amd(DC_CFG_MSR, msr);
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}
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}
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/* Erratum 94 ... */
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if (is_cpu_pre_d0()) {
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msr = rdmsr_amd(IC_CFG_MSR);
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@ -440,7 +440,7 @@ static inline void k8_errata(void)
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#endif
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#if CONFIG_K8_REV_F_SUPPORT == 0
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if (!is_cpu_pre_e0())
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if (!is_cpu_pre_e0())
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#endif
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{
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/* Erratum 110 ... */
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@ -478,12 +478,12 @@ static void model_fxx_init(device_t dev)
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#if CONFIG_K8_REV_F_SUPPORT == 1
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struct cpuinfo_x86 c;
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get_fms(&c, dev->device);
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#endif
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#if CONFIG_USBDEBUG_DIRECT
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if(!ehci_debug_addr)
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if(!ehci_debug_addr)
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ehci_debug_addr = get_ehci_debug();
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set_ehci_debug(0);
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#endif
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@ -501,7 +501,7 @@ static void model_fxx_init(device_t dev)
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model_fxx_update_microcode(dev->device);
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disable_cache();
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.hi = 0;
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@ -510,15 +510,15 @@ static void model_fxx_init(device_t dev)
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}
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k8_errata();
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/* Set SMMLOCK to avoid exploits messing with SMM */
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 0);
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wrmsr(HWCR_MSR, msr);
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/* Set the processor name string */
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init_processor_name();
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enable_cache();
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/* Enable the local cpu apics */
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@ -529,17 +529,17 @@ static void model_fxx_init(device_t dev)
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if(siblings>0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
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msr.lo = (siblings+1)<<16;
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msr.lo = (siblings+1)<<16;
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wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1<<(33-32);
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msr.hi |= 1<<(33-32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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}
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#endif
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