From 8a132065492bde4625675e572b39bfcbf09cdf29 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 21:44:00 +0200 Subject: [PATCH] cpu/intel/model_206ax/finalize.c: Drop dead code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code is not even being build-tested. Drop it before it grows moss. Change-Id: I76bf20bb2ec1cdd7ffee4430c80609978afaa1a4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43206 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/cpu/intel/model_206ax/finalize.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 10a95a2ce5..c7579f1764 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -16,24 +16,6 @@ void intel_model_206ax_finalize_smm(void) if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); -#ifdef LOCK_POWER_CONTROL_REGISTERS - /* - * Lock the power control registers. - * - * These registers can be left unlocked if modifying power - * limits from the OS is desirable. Modifying power limits - * from the OS can be especially useful for experimentation - * during early phases of system bringup while the thermal - * power envelope is being proven. - */ - - msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PKG_POWER_LIMIT, 63); - msr_set_bit(MSR_PP0_POWER_LIMIT, 31); - msr_set_bit(MSR_PP1_POWER_LIMIT, 31); -#endif - /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22);