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soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx 

Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.

TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.

Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-06-09 21:57:49 +05:30
parent 50134eccbd
commit 8a18bd8500
5 changed files with 67 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/intel/adlrvp/devicetree.cb
View File

@ -125,8 +125,9 @@ chip soc/intel/alderlake
# Enable EDP in PortA
register "DdiPortAConfig" = "1"
# Enable HDMI in Port B
register "DdiPortBDdc" = "1"
register "DdiPortBHpd" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "TcssAuxOri" = "0"

5
src/mainboard/intel/adlrvp/devicetree_m.cb
View File

@ -82,8 +82,9 @@ chip soc/intel/alderlake
# Enable EDP in PortA
register "DdiPortAConfig" = "1"
# Enable HDMI in Port B
register "DdiPortBDdc" = "1"
register "DdiPortBHpd" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "TcssAuxOri" = "0"

22
src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
View File

@ -118,21 +118,13 @@ chip soc/intel/alderlake
register "DdiPortAConfig" = "1" # eDP
register "DdiPortBConfig" = "0"
register "DdiPortAHpd" = "1"
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "0"
register "DdiPort1Hpd" = "1"
register "DdiPort2Hpd" = "1"
register "DdiPort3Hpd" = "0"
register "DdiPort4Hpd" = "0"
register "DdiPortADdc" = "0"
register "DdiPortBDdc" = "1"
register "DdiPortCDdc" = "0"
register "DdiPort1Ddc" = "0"
register "DdiPort2Ddc" = "0"
register "DdiPort3Ddc" = "0"
register "DdiPort4Ddc" = "0"
# Enable Display Port Configuration
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
[DDI_PORT_1] = DDI_ENABLE_HPD,
[DDI_PORT_2] = DDI_ENABLE_HPD,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+

36
src/soc/intel/alderlake/chip.h
View File

@ -26,6 +26,23 @@ enum soc_intel_alderlake_power_limits {
ADL_POWER_LIMITS_COUNT
};
/* Types of display ports */
enum ddi_ports {
DDI_PORT_A,
DDI_PORT_B,
DDI_PORT_C,
DDI_PORT_1,
DDI_PORT_2,
DDI_PORT_3,
DDI_PORT_4,
DDI_PORT_COUNT,
};
enum ddi_port_flags {
DDI_ENABLE_DDC = 1 << 0,
DDI_ENABLE_HPD = 1 << 1,
};
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */
@ -269,23 +286,8 @@ struct soc_intel_alderlake_config {
uint8_t DdiPortAConfig;
uint8_t DdiPortBConfig;
/* Enable(1)/Disable(0) HPD */
uint8_t DdiPortAHpd;
uint8_t DdiPortBHpd;
uint8_t DdiPortCHpd;
uint8_t DdiPort1Hpd;
uint8_t DdiPort2Hpd;
uint8_t DdiPort3Hpd;
uint8_t DdiPort4Hpd;
/* Enable(1)/Disable(0) DDC */
uint8_t DdiPortADdc;
uint8_t DdiPortBDdc;
uint8_t DdiPortCDdc;
uint8_t DdiPort1Ddc;
uint8_t DdiPort2Ddc;
uint8_t DdiPort3Ddc;
uint8_t DdiPort4Ddc;
/* Enable(1)/Disable(0) HPD/DDC */
uint8_t ddi_ports_config[DDI_PORT_COUNT];
/* Hybrid storage mode enable (1) / disable (0)
* This mode makes FSP detect Optane and NVME and set PCIe lane mode

57
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -68,11 +68,42 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_config *config)
{
unsigned int i;
const struct ddi_port_upds {
uint8_t *ddc;
uint8_t *hpd;
} ddi_port_upds[] = {
[DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd},
[DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd},
[DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd},
[DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd},
[DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd},
[DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
[DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
};
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
/* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0;
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 60MB. */
m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;
for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
*ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] &
DDI_ENABLE_DDC);
*ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] &
DDI_ENABLE_HPD);
}
} else {
/* IGD is disabled, skip IGD init in FSP. */
m_cfg->IgdDvmt50PreAlloc = 0;
/* DP port config */
m_cfg->DdiPortAConfig = 0;
m_cfg->DdiPortBConfig = 0;
for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
*ddi_port_upds[i].ddc = 0;
*ddi_port_upds[i].hpd = 0;
}
}
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->SaGv = config->SaGv;
@ -98,24 +129,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;
m_cfg->DdiPortAHpd = config->DdiPortAHpd;
m_cfg->DdiPortBHpd = config->DdiPortBHpd;
m_cfg->DdiPortCHpd = config->DdiPortCHpd;
m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
m_cfg->DdiPortADdc = config->DdiPortADdc;
m_cfg->DdiPortBDdc = config->DdiPortBDdc;
m_cfg->DdiPortCDdc = config->DdiPortCDdc;
m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
/* Image clock: disable all clocks for bypassing FSP pin mux */
memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));