mb/google/poppy/variants/nautilus: Update camera power enable GPIOs
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -261,7 +261,7 @@ chip soc/intel/skylake
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
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[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart0] = PchSerialIoPci,
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[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUart1] = PchSerialIoDisabled,
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
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}"
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@ -127,13 +127,13 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
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/* C7 : SM1DATA ==> NC */
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PAD_CFG_NC(GPP_C7),
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/* C8 : UART0_RXD ==> NC */
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PAD_CFG_NC(GPP_C8),
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/* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */
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PAD_CFG_GPO(GPP_C8, 0, DEEP),
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/* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */
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PAD_CFG_GPO(GPP_C9, 0, DEEP),
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/* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */
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/* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_UFCAM_EN */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
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PAD_CFG_GPI(GPP_C12, NONE, DEEP),
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@ -18,4 +18,8 @@
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#include <baseboard/gpio.h>
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/* Nautilus differs from baseboard in the GPIO used for EN_PP3300_DX_CAM. */
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#undef EN_PP3300_DX_CAM
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#define EN_PP3300_DX_CAM GPP_C8
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#endif /* __MAINBOARD_GPIO_H__ */
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