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mb/starlabs/lite/glkr: Organise USB ports by hardware port 

Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a7f50ca2b2001e83211e8eba56bfa929ecdfd74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes 2022-05-30 10:57:11 +01:00 committed by Felix Held
parent fe97c77cab
commit 8a4f076894
1 changed files with 7 additions and 8 deletions
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15
src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
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@ -89,22 +89,21 @@ chip soc/intel/apollolake
### USB 2.0 Devices
# Motherboard USB Type C
register "usb2_port[0]" = "PORT_EN(OC1)"
register "usb3_port[1]" = "PORT_EN(OC1)"
# Motherboard USB 3.0
register "usb2_port[1]" = "PORT_EN(OC0)"
register "usb3_port[0]" = "PORT_EN(OC0)"
# Daughterboard USB 3.0
register "usb2_port[3]" = "PORT_EN(OC1)"
# Daughterboard SD Card
register "usb2_port[5]" = "PORT_EN(OC_SKIP)"
register "usb3_port[3]" = "PORT_EN(OC1)"
# Bluetooth
register "usb2_port[6]" = "PORT_EN(OC_SKIP)"
### USB 3.0 Devices
# Motherboard USB 3.0
register "usb3_port[0]" = "PORT_EN(OC0)"
# Motherboard USB Type C
register "usb3_port[1]" = "PORT_EN(OC1)"
# Daughterboard USB 3.0
register "usb3_port[3]" = "PORT_EN(OC1)"
end
device pci 15.1 off end # XDCI
device pci 16.0 off end # I2C0