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Update MA785GM code 

This commit adds the following to MA785GM:

Refactor some alignment handling
Unify Local APIC address definitions
ACPI: More ../../.. removal
Remove old AMD fam10 fixme comment
amd/sb700: Move HAVE_HARD_RESET to southbridge

Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/922
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Alec Ari 2012-04-23 20:12:30 -05:00 committed by Peter Stuge
parent 1d89f14355
commit 8a527cfb49
5 changed files with 13 additions and 15 deletions
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1
src/mainboard/gigabyte/ma785gm/Kconfig
View File

@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT

20
src/mainboard/gigabyte/ma785gm/acpi_tables.c
View File

@ -110,7 +110,7 @@ unsigned long write_acpi_tables(unsigned long start)
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10;
start = ALIGN(start, 16);
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
@ -130,7 +130,7 @@ unsigned long write_acpi_tables(unsigned long start)
/*
* We explicitly add these tables later on:
*/
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
@ -138,7 +138,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
@ -146,7 +146,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_add_table(rsdp, madt);
/* SRAT */
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
@ -154,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_add_table(rsdp, srat);
/* SLIT */
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
@ -162,7 +162,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_add_table(rsdp, slit);
/* SSDT */
current = ( current + 0x0f) & -0x10;
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
@ -191,7 +191,7 @@ unsigned long write_acpi_tables(unsigned long start)
} else {
c = (u8) ('A' + i - 1 - 6);
}
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
switch (sysconf.hcid[i]) {
@ -220,7 +220,7 @@ unsigned long write_acpi_tables(unsigned long start)
#endif
/* DSDT */
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
@ -229,14 +229,14 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* FADT */
current = ( current + 0x07) & -0x08;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);

4
src/mainboard/gigabyte/ma785gm/dsdt.asl
View File

@ -27,7 +27,7 @@ DefinitionBlock (
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
/* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
@ -1162,7 +1162,7 @@ DefinitionBlock (
/* South Bridge */
Scope(\_SB) { /* Start \_SB scope */
#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
/* _SB.PCI0 */
/* Note: Only need HID on Primary Bus */

2
src/mainboard/gigabyte/ma785gm/mptable.c
View File

@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);

1
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb7xx_51xx_before_pci_init();
post_code(0x42);
printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}