soc/mediatek/mt8188: Add eDP support for firmware display
MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
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@ -33,6 +33,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
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ramstage-y += ../common/ddp.c ddp.c
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ramstage-y += ../common/ddp.c ddp.c
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ramstage-y += ../common/devapc.c devapc.c
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ramstage-y += ../common/devapc.c devapc.c
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ramstage-y += ../common/dfd.c
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ramstage-y += ../common/dfd.c
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ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
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ramstage-y += ../common/dpm.c
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ramstage-y += ../common/dpm.c
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ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
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ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
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ramstage-y += ../common/emi.c
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ramstage-y += ../common/emi.c
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@ -51,6 +52,7 @@ ramstage-y += ../common/usb.c usb.c
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BL31_MAKEARGS += PLAT=mt8188
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BL31_MAKEARGS += PLAT=mt8188
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8188/include
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8188/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/include
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MT8188_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8188
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MT8188_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8188
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#include <soc/addressmap.h>
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#include <soc/dp_intf.h>
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const struct mtk_dpintf dpintf_data = {
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.regs = (void *)(DP_INTF0_BASE),
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.color_format = MTK_DPINTF_COLOR_FORMAT_RGB,
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.yc_map = MTK_DPINTF_OUT_YC_MAP_RGB,
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.bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS,
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.channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
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.input_mode = MTK_DPINTF_INPUT_MODE_1P,
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};
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@ -96,9 +96,11 @@ enum {
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DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000,
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DISP_GAMMA0_BASE = IO_PHYS + 0x0C006000,
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DISP_DITHER0_BASE = IO_PHYS + 0x0C007000,
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DISP_DITHER0_BASE = IO_PHYS + 0x0C007000,
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DISP_OVL1_BASE = IO_PHYS + 0x0C00A000,
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DISP_OVL1_BASE = IO_PHYS + 0x0C00A000,
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DP_INTF0_BASE = IO_PHYS + 0x0C015000,
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DISP_MUTEX_BASE = IO_PHYS + 0x0C016000,
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DISP_MUTEX_BASE = IO_PHYS + 0x0C016000,
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DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000,
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DISP_POSTMASK0_BASE = IO_PHYS + 0x0C01A000,
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VDOSYS0_BASE = IO_PHYS + 0x0C01D000,
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VDOSYS0_BASE = IO_PHYS + 0x0C01D000,
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SMI_LARB0 = IO_PHYS + 0x0C022000,
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SMI_LARB0 = IO_PHYS + 0x0C022000,
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EDP_BASE = IO_PHYS + 0x0C500000,
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};
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};
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#endif
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#endif
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