From 8a6053b2bfb35fbe2a4398a2c299e9c12f26a8e3 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 2 Jul 2021 10:07:34 +0200
Subject: [PATCH] cpu/intel/car/p4: Add x86_64 support

Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/cpu/intel/car/p4-netburst/cache_as_ram.S | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 71ec9e34f7..9ac9e22c3e 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -359,6 +359,16 @@ fill_cache:
 	andl	$0xfffffff0, %esp
 	subl	$4, %esp
 
+#if ENV_X86_64
+	#include <cpu/x86/64bit/entry64.inc>
+
+	movd	%mm2, %rdi
+	shlq	$32, %rdi	/* BIST */
+	movd	%mm1, %rsi
+	or	%rsi, %rdi	/* tsc[63:32] */
+	movd	%mm0, %rsi	/* tsc[31:0] */
+
+#else
 	/* push TSC and BIST to stack */
 	movd	%mm0, %eax
 	pushl	%eax	/* BIST */
@@ -366,6 +376,7 @@ fill_cache:
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm1, %eax
 	pushl	%eax	/* tsc[31:0] */
+#endif
 
 before_c_entry:
 	post_code(0x2f)