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AMD/SB800: Define the GPP PCIe lane distribution 

Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
This fix was verified by openvoid on a AsRock E350M1 motherboard.

Change-Id: I0116c5f518e0d000be609013446e53da4112f586
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3104
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Dave Frodin 2013-04-17 18:21:09 -06:00 committed by Ronald G. Minnich
parent 6ceed0929d
commit 8a6f7a77f3
1 changed files with 3 additions and 3 deletions
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6
src/southbridge/amd/cimx/sb800/late.c
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@ -368,13 +368,13 @@ static void sb800_enable(device_t dev)
/* the first sb800 device */
switch (GPP_CFGMODE) { /* config the GPP PCIe ports */
case GPP_CFGMODE_X2200:
abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */
abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */
break;
case GPP_CFGMODE_X2110:
abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */
abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */
break;
case GPP_CFGMODE_X1111:
abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */
abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */
break;
case GPP_CFGMODE_X4000:
default: