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Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80s 

Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in
bootblock.

BUG=b:191370340
TEST: Build with & without the option enabled

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Martin Roth 2021-06-21 09:18:46 -06:00 committed by Patrick Georgi
parent b8bba6519e
commit 8a85a84fac
4 changed files with 7 additions and 9 deletions
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10
src/console/Kconfig
View File

@ -464,10 +464,12 @@ config NO_EARLY_BOOTBLOCK_POSTCODES
def_bool n def_bool n
help help
Some chipsets require that the routing for the port 80h POST Some chipsets require that the routing for the port 80h POST
code be configured before any POST codes are sent out. code be configured before any POST codes are sent out. If this is
This can be done in the boot block, but there are a couple of not done, the system can hang on the first POST code. This
POST codes that go out before the chipset's bootblock initialization initialization can be done in the boot block, but there are a couple
can happen. This option suppresses those POST codes. of POST codes that go out before the chipset's C bootblock
initialization can happen. This option suppresses all postcodes in
the early assembly code.
config HWBASE_DEBUG_CB config HWBASE_DEBUG_CB
bool bool

2
src/cpu/x86/entry16.S
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@ -43,9 +43,7 @@ _start16bit:
cli cli
/* Save the BIST result */ /* Save the BIST result */
movl %eax, %ebp movl %eax, %ebp
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_RESET_VECTOR_CORRECT) post_code(POST_RESET_VECTOR_CORRECT)
#endif
/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
* executing any further code. Even though paging is disabled we * executing any further code. Even though paging is disabled we

2
src/cpu/x86/entry32.S
View File

@ -31,9 +31,7 @@ bootblock_protected_mode_entry:
/* Save the BIST value */ /* Save the BIST value */
movl %eax, %ebp movl %eax, %ebp
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE) post_code(POST_ENTER_PROTECTED_MODE)
#endif
movw $ROM_DATA_SEG, %ax movw $ROM_DATA_SEG, %ax
movw %ax, %ds movw %ax, %ds

2
src/include/cpu/x86/post_code.h
View File

@ -3,7 +3,7 @@
#include <console/post_codes.h> #include <console/post_codes.h>
#if CONFIG(POST_IO) #if CONFIG(POST_IO) && !(ENV_BOOTBLOCK && CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
#define post_code(value) \ #define post_code(value) \
movb $value, %al; \ movb $value, %al; \
outb %al, $CONFIG_POST_IO_PORT outb %al, $CONFIG_POST_IO_PORT