clean up age old via epia target.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -622,7 +622,8 @@ config DEBUG_SMBUS
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|| NORTHBRIDGE_VIA_VX800 \
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|| NORTHBRIDGE_VIA_CX700 \
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|| NORTHBRIDGE_AMD_AMDK8 \
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|| NORTHBRIDGE_AMD_AMDFAM10)
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|| NORTHBRIDGE_AMD_AMDFAM10 \
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|| SOUTHBRIDGE_VIA_VT8231)
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help
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This option enables additional SMBus (and SPD) debug messages.
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@ -53,7 +53,7 @@ static void set_var_mtrr_x(
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}
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#endif
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static void cache_lbmem(int type)
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static inline void cache_lbmem(int type)
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{
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/* Enable caching for 0 - 1MB using variable mtrr */
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disable_cache();
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@ -118,7 +118,7 @@ static void early_mtrr_init(void)
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enable_cache();
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}
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static int early_mtrr_init_detected(void)
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static inline int early_mtrr_init_detected(void)
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{
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msr_t msr;
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/* See if MTRR's are enabled.
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@ -78,7 +78,6 @@ static void enable_shadow_ram(void)
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static void main(unsigned long bist)
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{
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unsigned long x;
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device_t dev;
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/*
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@ -13,7 +13,6 @@
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#include "cpu/x86/bist.h"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "lib/debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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#include "southbridge/via/vt8231/vt8231_early_serial.c"
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@ -76,10 +75,8 @@ static void enable_shadow_ram(void)
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pci_write_config8(dev, 0x63, shadowreg);
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}
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static void main(unsigned long bist)
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void main(unsigned long bist)
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{
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unsigned long x;
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if (bist == 0) {
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early_mtrr_init();
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}
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@ -47,7 +47,7 @@ it with the version available from LANL.
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#define DIMM_CL2 0
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#endif
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void dimms_read(unsigned long x)
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static void dimms_read(unsigned long x)
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{
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uint8_t c;
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unsigned long eax;
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@ -59,7 +59,7 @@ void dimms_read(unsigned long x)
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}
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}
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void dimms_write(int x)
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static void dimms_write(int x)
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{
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uint8_t c;
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unsigned long eax = x;
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@ -69,7 +69,8 @@ void dimms_write(int x)
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}
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}
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void dumpnorth(device_t north)
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#ifdef CONFIG_DEBUG_RAM_SETUP
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static void dumpnorth(device_t north)
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{
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unsigned int r, c;
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for (r = 0;; r += 16) {
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@ -84,11 +85,11 @@ void dumpnorth(device_t north)
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break;
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}
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}
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#endif
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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device_t north = (device_t) PCI_DEV(0, 0, 0);
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uint8_t c, r;
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print_err("vt8601 init starting\n");
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print_debug_hex32(north);
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@ -175,7 +176,7 @@ static unsigned long spd_module_size(unsigned char slot)
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* module. This is just a very early first cut at sizing.
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*/
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/* we may run out of registers ... */
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unsigned int banks, rows, cols, reg;
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unsigned int banks, rows, cols;
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unsigned int value = 0;
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/* unsigned int module = ((0x50 + slot) << 1) + 1; */
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unsigned int module = 0x50 + slot;
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@ -213,9 +214,9 @@ static unsigned long spd_module_size(unsigned char slot)
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}
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print_info("\n");
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return value;
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}
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#if 0
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static int spd_num_chips(unsigned char slot)
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{
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unsigned int module = 0x50 + slot;
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@ -226,6 +227,7 @@ static int spd_num_chips(unsigned char slot)
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width = 8;
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return 64 / width;
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}
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#endif
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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@ -275,7 +277,6 @@ static void set_ma_mapping(device_t north, int slot, int type)
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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unsigned char i;
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static const uint8_t ramregs[] = {
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0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
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};
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@ -12,11 +12,6 @@
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/* Base 8231 controller */
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static device_t lpc_dev;
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void hard_reset(void)
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{
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printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n");
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}
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static void keyboard_on(void)
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{
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unsigned char regval;
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@ -31,7 +31,6 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val)
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static void enable_vt8231_serial(void)
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{
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unsigned long x;
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uint8_t c;
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device_t dev;
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outb(6, 0x80);
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@ -107,6 +107,7 @@ static int smbus_wait_until_done(void)
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return loops ? 0 : -3;
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}
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#if 0
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void smbus_reset(void)
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{
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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@ -119,7 +120,9 @@ void smbus_reset(void)
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print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
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print_debug("\n");
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}
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#endif
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#if CONFIG_DEBUG_SMBUS
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static void smbus_print_error(unsigned char host_status_register)
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{
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@ -142,6 +145,7 @@ static void smbus_print_error(unsigned char host_status_register)
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print_err("Host Busy\n");
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}
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}
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#endif
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/*
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* Copied from intel/i82801dbm early smbus code - suggested by rgm.
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@ -150,7 +154,6 @@ static void smbus_print_error(unsigned char host_status_register)
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*/
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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unsigned char global_control_register;
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unsigned char global_status_register;
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unsigned char byte;
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@ -10,7 +10,6 @@
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/* PIRQ init
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*/
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void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
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static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
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@ -55,7 +54,6 @@ static void pci_routing_fixup(struct device *dev)
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static void vt8231_init(struct device *dev)
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{
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unsigned char enables;
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struct southbridge_via_vt8231_config *conf = dev->chip_info;
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printk(BIOS_DEBUG, "vt8231 init\n");
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@ -130,7 +128,7 @@ static void vt8231_init(struct device *dev)
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rtc_init(0);
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}
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void vt8231_read_resources(device_t dev)
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static void vt8231_read_resources(device_t dev)
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{
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struct resource *res;
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