diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index c3602c40b0..607604b78b 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -287,7 +287,8 @@ static void azalia_init(struct device *dev)
 	}
 }
 
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor,
+				 unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 7d44fba88b..7247132568 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -25,7 +25,7 @@
 
 typedef struct southbridge_intel_i82801ix_config config_t;
 
-static void i82801ix_enable_device(device_t dev)
+static void i82801ix_enable_device(struct device *dev)
 {
 	u32 reg32;
 
@@ -51,7 +51,7 @@ static void i82801ix_early_settings(const config_t *const info)
 
 static void i82801ix_pcie_init(const config_t *const info)
 {
-	device_t pciePort[6];
+	struct device *pciePort[6];
 	int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
 	u32 reg32;
 
@@ -86,7 +86,7 @@ static void i82801ix_pcie_init(const config_t *const info)
 
 	/* Set slot implemented, slot number and slot power limits. */
 	for (i = 0; i < 6; ++i) {
-		const device_t dev = pciePort[i];
+		struct device *const dev = pciePort[i];
 		u32 xcap = pci_read_config32(dev, D28Fx_XCAP);
 		if (info->pcie_slot_implemented & (1 << i))
 			xcap |=  PCI_EXP_FLAGS_SLOT;
@@ -115,10 +115,10 @@ static void i82801ix_pcie_init(const config_t *const info)
 
 static void i82801ix_ehci_init(void)
 {
-	const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
+	struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7));
 	if (!pciEHCI1)
 		die("EHCI controller (00:1d.7) not listed in devicetree.\n");
-	const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));
+	struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7));
 	if (!pciEHCI2)
 		die("EHCI controller (00:1a.7) not listed in devicetree.\n");
 
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index abc8667a67..76f16e7853 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -90,9 +90,9 @@ static void i82801ix_enable_serial_irqs(struct device *dev)
  * 0x80 - The PIRQ is not routed.
  */
 
-static void i82801ix_pirq_init(device_t dev)
+static void i82801ix_pirq_init(struct device *dev)
 {
-	device_t irq_dev;
+	struct device *irq_dev;
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
 
@@ -132,7 +132,7 @@ static void i82801ix_pirq_init(device_t dev)
 	}
 }
 
-static void i82801ix_gpi_routing(device_t dev)
+static void i82801ix_gpi_routing(struct device *dev)
 {
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
@@ -161,7 +161,7 @@ static void i82801ix_gpi_routing(device_t dev)
 	pci_write_config32(dev, D31F0_GPIO_ROUT, reg32);
 }
 
-static void i82801ix_power_options(device_t dev)
+static void i82801ix_power_options(struct device *dev)
 {
 	u8 reg8;
 	u16 reg16, pmbase;
@@ -293,7 +293,7 @@ static void i82801ix_power_options(device_t dev)
 	outl(reg32, pmbase + 0x10);
 }
 
-static void i82801ix_configure_cstates(device_t dev)
+static void i82801ix_configure_cstates(struct device *dev)
 {
 	u8 reg8;
 
@@ -469,7 +469,7 @@ static void lpc_init(struct device *dev)
 #endif
 }
 
-static void i82801ix_lpc_read_resources(device_t dev)
+static void i82801ix_lpc_read_resources(struct device *dev)
 {
 	/*
 	 *             I/O Resources
@@ -525,7 +525,7 @@ static void i82801ix_lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -536,7 +536,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
 {
 	global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
 
@@ -558,9 +558,9 @@ static void southbridge_inject_dsdt(device_t dev)
 	}
 }
 
-static void southbridge_fill_ssdt(device_t device)
+static void southbridge_fill_ssdt(struct device *device)
 {
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 	config_t *chip = dev->chip_info;
 
 	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c
index 5da2e49940..13f92f064a 100644
--- a/src/southbridge/intel/i82801ix/pci.c
+++ b/src/southbridge/intel/i82801ix/pci.c
@@ -43,7 +43,7 @@ static void pci_init(struct device *dev)
 	pci_write_config16(dev, PCI_SEC_STATUS, reg16);
 }
 
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	/* NOTE: 0x54 is not the default position! */
 	if (!vendor || !device) {
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 502e765773..04eb9b938b 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -94,7 +94,8 @@ static void pci_init(struct device *dev)
 	}
 }
 
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor,
+			       unsigned device)
 {
 	/* NOTE: 0x94 is not the default position! */
 	if (!vendor || !device) {
@@ -106,7 +107,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
-static void pch_pciexp_scan_bridge(device_t dev)
+static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
 
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index 8bfc476e8c..dcdeeb40d7 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -208,7 +208,8 @@ static void sata_init(struct device *const dev)
 	pci_write_config32(dev, 0x94, sclkcg);
 
 	if (is_mobile && config->sata_traffic_monitor) {
-		const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+		struct device *const lpc_dev = dev_find_slot(0,
+							    PCI_DEVFN(0x1f, 0));
 		if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF)
 							>> 3) & 3) == 3) {
 			u8 reg8 = pci_read_config8(dev, 0x9c);
@@ -224,7 +225,7 @@ static void sata_init(struct device *const dev)
 	sata_program_indexed(dev, is_mobile);
 }
 
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
 	const config_t *const config = dev->chip_info;
@@ -251,7 +252,8 @@ static void sata_enable(device_t dev)
 	pci_write_config16(dev, 0x90, map);
 }
 
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor,
+			       unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c
index ccfcddbec2..dc45510d01 100644
--- a/src/southbridge/intel/i82801ix/smbus.c
+++ b/src/southbridge/intel/i82801ix/smbus.c
@@ -25,7 +25,7 @@
 #include <southbridge/intel/common/smbus.h>
 #include "i82801ix.h"
 
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
 {
 	u16 reg16;
 
@@ -35,7 +35,7 @@ static void pch_smbus_init(device_t dev)
 	pci_write_config16(dev, 0x80, reg16);
 }
 
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
 {
 	u16 device;
 	struct resource *res;
@@ -48,7 +48,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
 	return do_smbus_read_byte(res->base, device, address);
 }
 
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
 {
 	u16 device;
 	struct resource *res;
@@ -66,7 +66,8 @@ static struct smbus_bus_operations lops_smbus_bus = {
 	.write_byte	= lsmbus_write_byte,
 };
 
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor,
+				unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -81,7 +82,7 @@ static struct pci_operations smbus_pci_ops = {
 	.set_subsystem    = smbus_set_subsystem,
 };
 
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
 {
 	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
 	res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 12cf89891f..5f40d2ec7c 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -50,7 +50,8 @@ static void thermal_init(struct device *dev)
 	pci_write_config32(dev, 0x10, 0);
 }
 
-static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void thermal_set_subsystem(struct device *dev, unsigned vendor,
+				  unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index 7719f16c1d..e386f825d9 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -33,7 +33,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
+				   unsigned device)
 {
 	u8 access_cntl;