intel/i945 intel/i82801gx: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove the pcie explicit accesses. The default config accesses use MMIO. Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3811 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
parent
9b143e1474
commit
8aa7e83994
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@ -529,9 +529,9 @@ static void i945_setup_pci_express_x16(void)
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reg16 |= DEVEN_D1F0;
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pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x208);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208);
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reg32 &= ~(1 << 8);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
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/* We have no success with querying the usual PCIe registers
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* for link setup success on the i945. Hence we assign a temporary
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@ -560,33 +560,33 @@ static void i945_setup_pci_express_x16(void)
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pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);
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pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
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reg32 &= ~(1 << 8);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
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MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
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/* Initialze PEG_CAP */
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reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
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reg16 |= (1 << 8);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
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/* Setup SLOTCAP */
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/* TODO: These values are mainboard dependent and should
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* be set from devicetree.cb.
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*/
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/* NOTE: SLOTCAP becomes RO after the first write! */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4);
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reg32 &= 0x0007ffff;
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reg32 &= 0xfffe007f;
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
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/* Wait for training to succeed */
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
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reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
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if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
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@ -597,21 +597,21 @@ static void i945_setup_pci_express_x16(void)
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printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
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reg32 &= ~(0xf << 1);
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reg32 |=1;
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32);
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reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
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reg16 |= (1 << 6);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
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reg16 &= ~(1 << 6);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
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printk(BIOS_DEBUG, "PCIe link training ...");
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timeout = 0x7ffff;
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while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
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while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
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reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
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if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
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@ -624,22 +624,22 @@ static void i945_setup_pci_express_x16(void)
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}
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}
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reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
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reg16 >>= 4;
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reg16 &= 0x3f;
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/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
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printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
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reg32 &= 0xfffffc00; /* clear [9:0] */
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if (reg16 == 1) {
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reg32 |= 0x32b;
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// TODO
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/* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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} else if (reg16 == 16) {
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reg32 |= 0x0f4;
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// TODO
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/* pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
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}
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reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
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@ -661,82 +661,82 @@ static void i945_setup_pci_express_x16(void)
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}
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/* Enable GPEs */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
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reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
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/* Virtual Channel Configuration: Only VC0 on PCIe x16 */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x114);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114);
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reg32 &= 0xffffff01;
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
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/* Extended VC count */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x104);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104);
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reg32 &= ~(7 << 0);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);
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/* Active State Power Management ASPM */
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/* TODO */
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/* Clear error bits */
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff);
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pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff);
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/* Program R/WO registers */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x308);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x314);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x324);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x328);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32);
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reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), 0xb4);
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pcie_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8);
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reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4);
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pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8);
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/* Additional PCIe graphics setup */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 |= (3 << 26);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 |= (3 << 24);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
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reg32 |= (1 << 5);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200);
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reg32 &= ~(3 << 26);
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reg32 |= (2 << 26);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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if (i945_silicon_revision() >= 2) {
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reg32 |= (1 << 12);
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} else {
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reg32 &= ~(1 << 12);
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}
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
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reg32 &= ~(1 << 31);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xfc);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc);
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reg32 |= (1 << 31);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32);
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if (i945_silicon_revision() >= 3) {
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static const u32 reglist[] = {
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@ -747,21 +747,21 @@ static void i945_setup_pci_express_x16(void)
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int i;
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for (i=0; i<ARRAY_SIZE(reglist); i++) {
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]);
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reg32 &= 0x0fffffff;
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reg32 |= (2 << 28);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32);
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}
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}
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if (i945_silicon_revision() <= 2 ) {
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/* Set voltage specific parameters */
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
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reg32 &= (0xf << 4); /* Default case 1.05V */
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if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */
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reg32 |= (7 << 4);
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}
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
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}
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return;
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@ -772,21 +772,21 @@ disable_pciexpress_x16_link:
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MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
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reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
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reg16 |= (1 << 6);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
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pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
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reg32 |= (1 << 8);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
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reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
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reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
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reg16 &= ~(1 << 6);
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pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
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pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
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printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
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timeout = 0x7fffff;
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for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
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for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
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(reg32 & 0x000f0000) && --timeout;) ;
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if (!timeout)
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printk(BIOS_DEBUG, "timeout!\n");
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@ -836,10 +836,10 @@ static void i945_setup_root_complex_topology(void)
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/* PCI Express x16 Port Root Topology */
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if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) {
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR);
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reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR);
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150);
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reg32 |= (1 << 0);
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pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32);
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pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32);
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}
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}
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@ -224,39 +224,35 @@ static void azalia_init(struct device *dev)
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u8 reg8;
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u32 reg32;
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#if CONFIG_MMCONF_SUPPORT
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// ESD
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reg32 = pci_mmio_read_config32(dev, 0x134);
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reg32 = pci_read_config32(dev, 0x134);
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reg32 &= 0xff00ffff;
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reg32 |= (2 << 16);
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pci_mmio_write_config32(dev, 0x134, reg32);
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pci_write_config32(dev, 0x134, reg32);
|
||||
|
||||
// Link1 description
|
||||
reg32 = pci_mmio_read_config32(dev, 0x140);
|
||||
reg32 = pci_read_config32(dev, 0x140);
|
||||
reg32 &= 0xff00ffff;
|
||||
reg32 |= (2 << 16);
|
||||
pci_mmio_write_config32(dev, 0x140, reg32);
|
||||
pci_write_config32(dev, 0x140, reg32);
|
||||
|
||||
// Port VC0 Resource Control Register
|
||||
reg32 = pci_mmio_read_config32(dev, 0x114);
|
||||
reg32 = pci_read_config32(dev, 0x114);
|
||||
reg32 &= 0xffffff00;
|
||||
reg32 |= 1;
|
||||
pci_mmio_write_config32(dev, 0x114, reg32);
|
||||
pci_write_config32(dev, 0x114, reg32);
|
||||
|
||||
// VCi traffic class
|
||||
reg8 = pci_mmio_read_config8(dev, 0x44);
|
||||
reg8 = pci_read_config8(dev, 0x44);
|
||||
reg8 |= (7 << 0); // TC7
|
||||
pci_mmio_write_config8(dev, 0x44, reg8);
|
||||
pci_write_config8(dev, 0x44, reg8);
|
||||
|
||||
// VCi Resource Control
|
||||
reg32 = pci_mmio_read_config32(dev, 0x120);
|
||||
reg32 = pci_read_config32(dev, 0x120);
|
||||
reg32 |= (1 << 31);
|
||||
reg32 |= (1 << 24); // VCi ID
|
||||
reg32 |= (0x80 << 0); // VCi map
|
||||
pci_mmio_write_config32(dev, 0x120, reg32);
|
||||
#else
|
||||
#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
|
||||
#endif
|
||||
pci_write_config32(dev, 0x120, reg32);
|
||||
|
||||
/* Set Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
|
|
|
|||
|
|
@ -23,6 +23,10 @@
|
|||
#include <device/pci.h>
|
||||
#include "i82801gx.h"
|
||||
|
||||
#if !CONFIG_MMCONF_SUPPORT_DEFAULT
|
||||
#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT
|
||||
#endif
|
||||
|
||||
void i82801gx_enable(device_t dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
|
|
|||
|
|
@ -55,20 +55,17 @@ static void pci_init(struct device *dev)
|
|||
reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
|
||||
pci_write_config32(dev, 0xe1, reg32);
|
||||
|
||||
#if CONFIG_MMCONF_SUPPORT
|
||||
/* Set VC0 transaction class */
|
||||
reg32 = pci_mmio_read_config32(dev, 0x114);
|
||||
reg32 = pci_read_config32(dev, 0x114);
|
||||
reg32 &= 0xffffff00;
|
||||
reg32 |= 1;
|
||||
pci_mmio_write_config32(dev, 0x114, reg32);
|
||||
pci_write_config32(dev, 0x114, reg32);
|
||||
|
||||
/* Mask completion timeouts */
|
||||
reg32 = pci_mmio_read_config32(dev, 0x148);
|
||||
reg32 = pci_read_config32(dev, 0x148);
|
||||
reg32 |= (1 << 14);
|
||||
pci_mmio_write_config32(dev, 0x148, reg32);
|
||||
#else
|
||||
#error "MMIO needed for ICH7 PCIe"
|
||||
#endif
|
||||
pci_write_config32(dev, 0x148, reg32);
|
||||
|
||||
/* Enable common clock configuration */
|
||||
// Are there cases when we don't want that?
|
||||
reg16 = pci_read_config16(dev, 0x50);
|
||||
|
|
|
|||
|
|
@ -319,13 +319,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
|
|||
/* Always set the flag in case CMOS was changed on runtime. For
|
||||
* "KEEP", switch to "OFF" - KEEP is software emulated
|
||||
*/
|
||||
reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
|
||||
if (s5pwr == MAINBOARD_POWER_ON) {
|
||||
reg8 &= ~1;
|
||||
} else {
|
||||
reg8 |= 1;
|
||||
}
|
||||
pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
|
||||
|
||||
/* also iterates over all bridges on bus 0 */
|
||||
busmaster_disable_on_bus(0);
|
||||
|
|
@ -494,7 +494,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
|
|||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||||
u8 bios_cntl;
|
||||
|
||||
bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
|
||||
if (bios_cntl & 1) {
|
||||
/* BWE is RW, so the SMI was caused by a
|
||||
|
|
@ -508,7 +508,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
|
|||
* box.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "Switching back to RO\n");
|
||||
pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
|
||||
} /* No else for now? */
|
||||
} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
|
||||
/* Handle TCO timeout */
|
||||
|
|
@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
|
|||
u32 smi_sts;
|
||||
|
||||
/* Update global variable pmbase */
|
||||
pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
|
||||
/* We need to clear the SMI status registers, or we won't see what's
|
||||
* happening in the following calls.
|
||||
|
|
|
|||
Loading…
Reference in New Issue