sb/intel/common: Fix conflicting OIC register definition

Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).

This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.

Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/google/butterfly/romstage.c

@@ -96,9 +96,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);

src/mainboard/google/link/romstage.c

@@ -104,9 +104,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }
 
 static uint8_t *locate_spd(void)

src/mainboard/google/parrot/romstage.c

@@ -95,9 +95,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);

src/mainboard/google/stout/romstage.c

@@ -101,9 +101,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);

src/mainboard/samsung/lumpy/romstage.c

@@ -103,9 +103,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }
 
 static const uint8_t *locate_spd(void)

src/mainboard/samsung/stumpy/romstage.c

@@ -112,9 +112,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }
 
 static void setup_sio_gpios(void)

src/southbridge/intel/bd82x6x/early_rcba.c

@@ -60,9 +60,9 @@ southbridge_configure_default_intmap(void)
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
+	RCBA16(EOIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
+	(void) RCBA16(EOIC);
 }
 
 void

src/southbridge/intel/common/rcba.h

@@ -147,6 +147,7 @@
 #define D20IR		0x3160	/* 16bit */
 #define D19IR		0x3168	/* 16bit */
 
+#define EOIC		0x31fe	/* 16bit */
 #define OIC		0x31ff	/*  8bit */
 
 #define DIR_ROUTE(x, a, b, c, d) \