diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 2e3591f4a6..46c2d417a5 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -44,6 +44,11 @@ struct soc_intel_tigerlake_config {
 
 	/* Enable S0iX support */
 	int s0ix_enable;
+	/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
+	uint8_t TcssD3HotEnable;
+	/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
+	uint8_t TcssD3ColdEnable;
+
 	/* Enable DPTF support */
 	int dptf_enable;
 
@@ -216,11 +221,11 @@ struct soc_intel_tigerlake_config {
 		FORCE_ENABLE,
 	} CnviBtAudioOffload;
 
-	/* Tcss USB */
+	/* TCSS USB */
 	uint8_t TcssXhciEn;
 	uint8_t TcssXdciEn;
 
-	/* Tcss DMA */
+	/* TCSS DMA */
 	uint8_t TcssDma0En;
 	uint8_t TcssDma1En;
 
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 0c67105300..850cdbd169 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -101,6 +101,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
 	}
 
+	/* D3Hot and D3Cold for TCSS */
+	params->D3HotEnable = config->TcssD3HotEnable;
+	params->D3ColdEnable = config->TcssD3ColdEnable;
+
 	params->TcssAuxOri = config->TcssAuxOri;
 	for (i = 0; i < 8; i++)
 		params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i];