*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
2560dbdd50
commit
8abb054c0e
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@ -9,7 +9,7 @@
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#include <string.h>
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#include <string.h>
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#include <bitops.h>
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#include <bitops.h>
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#include "chip.h"
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#include "chip.h"
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#if 0
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struct mem_range *sizeram(void)
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struct mem_range *sizeram(void)
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{
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{
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static struct mem_range mem[4];
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static struct mem_range mem[4];
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@ -113,7 +113,269 @@ struct mem_range *sizeram(void)
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return mem;
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return mem;
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}
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}
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#endif
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struct chip_operations northbridge_intel_e7501_control = {
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
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.name = "intel E7501 Northbridge",
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned reg;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, 0);
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resource->base = 0x400;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO;
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_IO, IORESOURCE_IO);
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/* Initialize the system wide prefetchable memory resources constraints */
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resource = new_resource(dev, 1);
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_MEM | IORESOURCE_PREFETCH,
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IORESOURCE_MEM | IORESOURCE_PREFETCH);
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, 2);
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM;
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_MEM | IORESOURCE_PREFETCH,
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IORESOURCE_MEM);
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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struct resource *io, *mem1, *mem2;
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struct resource *resource, *last;
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unsigned long mmio_basek;
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uint32_t pci_tolm;
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int idx;
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uint8_t drb;
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unsigned basek, sizek;
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device_t dev_memctrl;
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#if 0
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/* Place the IO devices somewhere safe */
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io = find_resource(dev, 0);
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io->base = DEVICE_IO_START;
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#endif
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#if 1
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/* Now reallocate the pci resources memory with the
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* highest addresses I can manage.
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*/
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mem1 = find_resource(dev, 1);
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mem2 = find_resource(dev, 2);
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#if 1
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printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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/* See if both resources have roughly the same limits */
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
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((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
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{
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/* If so place the one with the most stringent alignment first
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*/
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if (mem2->align > mem1->align) {
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struct resource *tmp;
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tmp = mem1;
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mem1 = mem2;
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mem2 = tmp;
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}
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/* Now place the memory as high up as it will go */
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mem2->base = resource_max(mem2);
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mem1->limit = mem2->base - 1;
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mem1->base = resource_max(mem1);
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}
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else {
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/* Place the resources as high up as they will go */
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mem2->base = resource_max(mem2);
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mem1->base = resource_max(mem1);
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}
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#if 1
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printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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#endif
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pci_tolm = 0xffffffffUL;
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last = &dev->resource[dev->resources];
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for(resource = &dev->resource[0]; resource < last; resource++)
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{
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#if 1
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resource->flags |= IORESOURCE_ASSIGNED;
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resource->flags &= ~IORESOURCE_STORED;
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#endif
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compute_allocate_resource(&dev->link[0], resource,
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BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
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resource->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, resource, "");
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if ((resource->flags & IORESOURCE_MEM) &&
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(pci_tolm > resource->base))
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{
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pci_tolm = resource->base;
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}
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}
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#warning "FIXME handle interleaved nodes"
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mmio_basek = pci_tolm >> 10;
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/* Round mmio_basek to something the processor can support */
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mmio_basek &= ~((1 << 6) -1);
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#if 1
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#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
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/* Round the mmio hold to 64M */
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mmio_basek &= ~((64*1024) - 1);
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#endif
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dev_memctrl = dev_find_slot(0, 0); // d0f0
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drb = pci_read_config8(dev_memctrl, 0x67);
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idx = 10;
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basek = 0;
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sizek = 640;
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ram_resource(dev, idx++, basek, sizek);
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basek = 768;
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sizek = mmio_basek - basek;
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ram_resource(dev, idx++, basek, sizek);
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if ((drb << 16) > mmio_basek) {
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/* We don't need to consider the remap window
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* here because we put it immediately after the
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* rest of ram.
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* All we must do is calculate the amount
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* of unused memory and report it at 4GB.
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*/
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basek = 4096*1024;
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sizek = (drb << 16) - mmio_basek;
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ram_resource(dev, idx++, basek, sizek);
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}
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
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{
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struct bus *cpu_bus;
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unsigned reg;
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int i;
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/* Find which cpus are present */
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cpu_bus = &dev->link[0];
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for(i = 0; i < 7; i+=6) {
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device_t dev, cpu;
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struct device_path cpu_path;
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#if 0
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//How to identify Intel CPU
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/* Find the cpu's memory controller */
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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#endif
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/* Build the cpu device path */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.u.apic.apic_id = i;
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/* See if I can find the cpu */
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cpu = find_dev_path(cpu_bus, &cpu_path);
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#if 0
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/* Enable the cpu if I have the processor */
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if (dev && dev->enabled) {
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if (!cpu) {
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cpu = alloc_dev(cpu_bus, &cpu_path);
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}
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if (cpu) {
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cpu->enabled = 1;
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}
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}
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/* Disable the cpu if I don't have the processor */
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if (cpu && (!dev || !dev->enabled)) {
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cpu->enabled = 0;
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}
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#else
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cpu->enabled = 1;
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#endif
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/* Report what I have done */
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if (cpu) {
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printk_debug("CPU: %s %s\n",
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dev_path(cpu), cpu->enabled?"enabled":"disabled");
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}
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}
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return max;
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}
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = cpu_bus_scan,
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};
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static void enable_dev(struct device *dev)
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{
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struct device_path path;
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_e7501_ops = {
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.name = "intel E7501 Northbridge",
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.enable_dev = enable_dev,
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};
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};
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