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mainboard/google/poppy: Enable separate MRC cache for recovery mode 

Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.

BUG=b:37682566
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.

Change-Id: I4c748a316436001c5a33754084ab4a74243e21df
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-04-25 22:48:31 -07:00 committed by Furquan Shaikh
parent 13c6dbf8d3
commit 8ac19c8629
2 changed files with 20 additions and 13 deletions
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2
src/mainboard/google/poppy/Kconfig
View File

@ -72,6 +72,8 @@ config VARIANT_DIR
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
select VBOOT_LID_SWITCH
config DRIVER_TPM_SPI_BUS

27
src/mainboard/google/poppy/chromeos.fmd
View File

@ -4,24 +4,29 @@ FLASH@0xff000000 0x1000000 {
SI_ME@0x1000 0x1ff000
}
SI_BIOS@0x200000 0xe00000 {
RW_SECTION_A@0x0 0x3f0000 {
RW_SECTION_A@0x0 0x3e8000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x3dffc0
RW_FWID_A@0x3effc0 0x40
FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
RW_FWID_A@0x3e7fc0 0x40
}
RW_SECTION_B@0x3f0000 0x3f0000 {
RW_SECTION_B@0x3e8000 0x3e8000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x3dffc0
RW_FWID_B@0x3effc0 0x40
FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
RW_FWID_B@0x3e7fc0 0x40
}
RW_MRC_CACHE@0x7e0000 0x10000
RW_ELOG@0x7f0000 0x4000
RW_SHARED@0x7f4000 0x4000 {
RW_MISC@0x7d0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD@0x7f8000 0x2000
RW_NVRAM@0x7fa000 0x6000
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x800000 0x200000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000