nb/intel/gm45/iommu.c: Fix regression when updating PCI command
Commit5ac723e
(nb/intel: Fix 16-bit read/write PCI_COMMAND register) uses `pci_read_config8` to read the PCI command register, which does not correspond with what has been stated in the commit message. Moreover, it potentially breaks things, as the upper byte of the PCI command register is now being cleared. So, restore the original behaviour of the code, using 16-bit accesses. Fixes:5ac723e
(nb/intel: Fix 16-bit read/write PCI_COMMAND register) Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -43,9 +43,7 @@ void init_iommu()
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memset(bar, 0, 2<<20);
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/* and now disable again */
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u16 cmd = pci_read_config8(igd, PCI_COMMAND);
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cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config16(igd, PCI_COMMAND, cmd);
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pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
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pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0);
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}
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