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Unify use of bool config variables 

e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS

This will make it easier to switch over to use the config_enabled()
macro later on.

Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Stefan Reinauer 2012-11-16 13:34:48 -08:00 committed by Patrick Georgi
parent 82ecf4c582
commit 8ada1526df
21 changed files with 36 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/x86/lib/c_start.S
View File

@ -82,7 +82,7 @@ _start:
/* Restore the stack location */
movl %ebp, %esp
#if CONFIG_GDB_WAIT == 1
#if CONFIG_GDB_WAIT
call gdb_stub_breakpoint
#endif
/* The boot_complete flag has already been pushed */
@ -235,7 +235,7 @@ int_hand:
iret
#if CONFIG_GDB_WAIT == 1
#if CONFIG_GDB_WAIT
.globl gdb_stub_breakpoint
gdb_stub_breakpoint:

6
src/cpu/amd/agesa/family15tn/model_15_init.c
View File

@ -62,7 +62,7 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@ -90,7 +90,7 @@ static void model_15_init(device_t dev)
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type == 3)
restore_mtrr();
#endif
@ -109,7 +109,7 @@ static void model_15_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {

2
src/devices/pci_device.c
View File

@ -663,7 +663,7 @@ int oprom_is_loaded = 0;
/** Default handler: only runs the relevant PCI BIOS. */
void pci_dev_init(struct device *dev)
{
#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN
struct rom_header *rom, *ram;
if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */

2
src/include/cpu/x86/lapic.h
View File

@ -52,7 +52,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
}
#ifndef __ROMCC__
#if CONFIG_AP_IN_SIPI_WAIT != 1
#if !CONFIG_AP_IN_SIPI_WAIT
/* If we need to go back to sipi wait, we use the long non-inlined version of
* this function in lapic_cpu_init.c
*/

2
src/mainboard/amd/parmer/agesawrapper.c
View File

@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask (
return (UINT32)Status;
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
UINT32 agesawrapper_amdinitresume(VOID)
{

4
src/mainboard/amd/parmer/get_bus_conf.c
View File

@ -47,7 +47,7 @@ u32 sbdn_sb800;
static u32 get_bus_conf_done = 0;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
void get_bus_conf(void)
@ -78,7 +78,7 @@ void get_bus_conf(void)
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
if(status) {

2
src/mainboard/amd/parmer/mainboard.c
View File

@ -39,7 +39,7 @@ static void parmer_enable(device_t dev)
* The mainboard is the first place that we get control in ramstage. Check
* for S3 resume and call the approriate AGESA/CIMx resume functions.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
if (acpi_slp_type == 3)
agesawrapper_fchs3earlyrestore();

2
src/mainboard/amd/parmer/romstage.c
View File

@ -44,7 +44,7 @@ void disable_cache_as_ram(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
val = agesawrapper_amdinitmmio();

2
src/mainboard/amd/thatcher/agesawrapper.c
View File

@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask (
return (UINT32)Status;
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
UINT32 agesawrapper_amdinitresume(VOID)
{

4
src/mainboard/amd/thatcher/get_bus_conf.c
View File

@ -47,7 +47,7 @@ u32 sbdn_sb800;
static u32 get_bus_conf_done = 0;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
void get_bus_conf(void)
@ -78,7 +78,7 @@ void get_bus_conf(void)
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
if(status) {

2
src/mainboard/amd/thatcher/mainboard.c
View File

@ -55,7 +55,7 @@ static void thatcher_enable(device_t dev)
* The mainboard is the first place that we get control in ramstage. Check
* for S3 resume and call the approriate AGESA/CIMx resume functions.
*/
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
if (acpi_slp_type == 3)
agesawrapper_fchs3earlyrestore();

2
src/mainboard/amd/thatcher/romstage.c
View File

@ -49,7 +49,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 byte;
device_t dev;
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
val = agesawrapper_amdinitmmio();

2
src/mainboard/asus/m4a785-m/romstage.c
View File

@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
#ifndef CONFIG_BOARD_ASUS_M4A785TM
#if !CONFIG_BOARD_ASUS_M4A785TM
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual override */
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {

4
src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
View File

@ -36,10 +36,6 @@
#define DUMP_ACPI_TABLES 0
#ifndef CONFIG_LINT01_CONVERSION
#define CONFIG_LINT01_CONVERSION 1
#endif
extern u16 pm_base;
/*

6
src/mainboard/tyan/s8226/buildOpts.c
View File

@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
}
};
#if CONFIG_HT3_SUPPORT == 1
#if CONFIG_HT3_SUPPORT
/**
* The socket and link match values are platform specific
*
@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1)
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1)
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/

4
src/mainboard/tyan/s8226/rd890_cfg.h
View File

@ -31,10 +31,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif

4
src/southbridge/amd/agesa/hudson/early_setup.c
View File

@ -79,7 +79,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
@ -89,7 +89,7 @@ int acpi_get_sleep_type(void)
}
#endif
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void)
{
return (acpi_get_sleep_type() == 3);

2
src/southbridge/amd/agesa/hudson/hudson.c
View File

@ -30,7 +30,7 @@
#include "hudson.h"
#include "smbus.h"
#if CONFIG_HAVE_ACPI_RESUME == 1
#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);

2
src/southbridge/amd/cs5530/vga.c
View File

@ -492,4 +492,4 @@ static const struct pci_driver vga_pci_driver __pci_driver = {
.device = PCI_DEVICE_ID_CYRIX_5530_VIDEO,
};
#endif /* #if CONFIG_GX1_VIDEO == 1 */
#endif /* #if CONFIG_GX1_VIDEO */

14
src/southbridge/amd/rs780/early_setup.c
View File

@ -147,7 +147,7 @@ static u8 is_famly10(void)
return (cpuid_eax(1) & 0xff00000) != 0;
}
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
static u8 l3_cache(void)
{
return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
@ -246,7 +246,7 @@ static void rs780_htinit(void)
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
/* HT3 mode, RPR 8.4.3 */
set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
@ -282,11 +282,11 @@ static void rs780_htinit(void)
/* Sets Training 0 Time. See T0Time table for encodings */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
/* TODO: */
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
}
}
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */
#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
/*******************************************************
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
@ -340,9 +340,9 @@ static void k8_optimization(void)
}
#else
#define k8_optimization() do{}while(0)
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
static void fam10_optimization(void)
{
device_t cpu_f0, cpu_f2, cpu_f3;
@ -405,7 +405,7 @@ static void fam10_optimization(void)
}
#else
#define fam10_optimization() do{}while(0)
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
/*****************************************
* rs780_por_pcicfg_init()

4
src/southbridge/amd/sr5650/early_setup.c
View File

@ -266,7 +266,7 @@ void sr5650_htinit(void)
//set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
/* HT Buffer Allocation for Ganged Links!!! */
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
}
}
@ -299,7 +299,7 @@ void fam10_optimization(void)
}
#else
#define fam10_optimization() do{}while(0)
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************
* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE