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mb/google/hatch: Enable Host Bridge/CSME/PMC/P2SB/SMBus 

* Enable host bridge.
* Enable CSME.
* Enable Power Management Controller.
* Enable Primary to Side Band Bridge Controller.
* Enable SmBus Controller.

BUG=b:120914069
BRANCH=None
TEST=code compiles with the changes

Change-Id: I2fbf0ece845a7114ce5ab7f6482a935d9275deee
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Rizwan Qureshi 2018-12-28 12:29:56 +05:30 committed by Subrata Banik
parent fba0320842
commit 8ae5418853
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -41,7 +41,7 @@ chip soc/intel/cannonlake
register "SkipExtGfxScan" = "1"
device domain 0 on
device pci 00.0 off end # Host Bridge
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
device pci 12.0 off end # Thermal Subsystem
@ -61,7 +61,7 @@ chip soc/intel/cannonlake
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
@ -97,10 +97,10 @@ chip soc/intel/cannonlake
end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on end # LPC/eSPI
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
device pci 1f.3 off end # Intel HDA
device pci 1f.4 off end # SMBus
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end