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lenovo/x60/i915.c: Use define for `BSM` 

Although it builds without any further changes, including the header

	src/northbridge/intel/i945/i945.h

where `BSM` is defined, would be useful. Unfortunately that conflicts
with the already included header `southbridge/intel/bd82x6x/pch.h`,
so it is left as is.

Change-Id: I7c0a795338c34038169e082446907987364a0e88
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5932
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Paul Menzel 2014-06-05 08:50:17 +02:00 committed by Patrick Georgi
parent 9238c11be4
commit 8aeab56b10
1 changed files with 1 additions and 1 deletions
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src/mainboard/lenovo/x60/i915.c
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@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase)
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
PGETBL_save |= PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED;
PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */ PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0); write32(mmiobase + GFX_FLSH_CNTL, 0);