- Update raminit.c so it works properly for multiple cpus

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman 2003-08-01 02:52:35 +00:00
parent 5f7fc31d70
commit 8aeb2a4dbf
1 changed files with 526 additions and 572 deletions

View File

@ -973,6 +973,7 @@ static int is_opteron(const struct mem_controller *ctrl)
* FIXME Testing dual channel capability is correct for now
* but a beter test is probably required.
*/
#warning "FIXME implement a better test for opterons"
uint32_t nbcap;
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
return !!(nbcap & NBCAP_128Bit);
@ -1122,22 +1123,6 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
set_dimm_size(ctrl, sz, i);
}
}
static void fill_last(unsigned long node_id,unsigned long base)
{
//BY LYH //Fill next base reg with right value
unsigned i;
unsigned base_reg;
base &=0xffff0000;
device_t device;
for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
+= PCI_DEV(0, 1, 0)) {
for(i=node_id+1;i<=7;i++) {
base_reg=0x40+(i<<3);
pci_write_config32(device,base_reg,base);
}
}
//BY LYH END
}
static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned long base_k, unsigned long limit_k)
@ -1148,8 +1133,8 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned base;
unsigned index;
unsigned limit_reg, base_reg;
device_t device;
node_id = ctrl->node_id;
index = (node_id << 3);
limit = (limit_k << 2);
@ -1166,7 +1151,6 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
pci_write_config32(device, limit_reg, limit);
pci_write_config32(device, base_reg, base);
}
}
static void set_top_mem(unsigned tom_k)
@ -1207,17 +1191,6 @@ static void order_dimms(const struct mem_controller *ctrl)
/* Compute the memory base address address */
base_k = 0;
for(node_id = 0; node_id < ctrl->node_id; node_id++) {
uint32_t limit, base;
unsigned index;
index = node_id << 3;
base = pci_read_config32(ctrl->f1, 0x40 + index);
/* Only look at the limit if the base is enabled */
if ((base & 3) == 3) {
limit = pci_read_config32(ctrl->f1, 0x44 + index);
base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
}
}
/* Remember which registers we have used in the high 8 bits of tom */
tom = base_k >> 15;
for(;;) {
@ -1257,30 +1230,11 @@ static void order_dimms(const struct mem_controller *ctrl)
/* Remember the dimm size */
size = csbase >> 21;
/* If this is the first chip select, round base_k to
* be a multiple of it's size. Then set tom to equal
* base_k.
* I assume that size is a power of two.
*/
if ((tom & 0xff000000) == 0) {
unsigned size_k;
size_k = size << 15;
base_k = (base_k + size_k -1) & ~(size_k -1);
tom = base_k >> 15;
}
/* Remember I have used this register */
tom |= (1 << (canidate + 24));
/* Recompute the cs base register value */
#if 1 // BY LYH Need to count from 0 for every memory controller
csbase = ((tom - (base_k>>15))<< 21) | 1;
// print_debug("csbase=");
// print_debug_hex32(csbase);
// print_debug("\r\n");
#else //BY LYH END
csbase = (tom << 21) | 1;
#endif
/* Increment the top of memory */
tom += size;
@ -1297,6 +1251,21 @@ static void order_dimms(const struct mem_controller *ctrl)
}
tom_k = (tom & ~0xff000000) << 15;
/* Compute the memory base address */
base_k = 0;
for(node_id = 0; node_id < ctrl->node_id; node_id++) {
uint32_t limit, base;
unsigned index;
index = node_id << 3;
base = pci_read_config32(ctrl->f1, 0x40 + index);
/* Only look at the limit if the base is enabled */
if ((base & 3) == 3) {
limit = pci_read_config32(ctrl->f1, 0x44 + index);
base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
}
}
tom_k += base_k;
#if 0
print_debug("tom: ");
print_debug_hex32(tom);
@ -1307,18 +1276,6 @@ static void order_dimms(const struct mem_controller *ctrl)
print_debug("\r\n");
#endif
route_dram_accesses(ctrl, base_k, tom_k);
//BY LYH
fill_last(ctrl->node_id, tom_k<<2);
//BY LYH END
#if 0 //BY LYH
dump_pci_device(PCI_DEV(0, 0x18, 1));
// if(ctrl->node_id==1) {
// pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
// }
#endif
set_top_mem(tom_k);
}
@ -2267,9 +2224,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug_hex32(dcl);
print_debug("\r\n");
#endif
#if 0
dcl &= ~DCL_DimmEccEn;
#endif
#warning "FIXME set the ECC type to perform"
#warning "FIXME initialize the scrub registers"
#if 1
@ -2303,7 +2257,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
} else {
print_debug(" done\r\n");
}
#if 1
#if 0
if (dcl & DCL_DimmEccEn) {
print_debug("Clearing memory: ");
loops = 0;