- Update raminit.c so it works properly for multiple cpus
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
5f7fc31d70
commit
8aeb2a4dbf
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@ -973,6 +973,7 @@ static int is_opteron(const struct mem_controller *ctrl)
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* FIXME Testing dual channel capability is correct for now
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* but a beter test is probably required.
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*/
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#warning "FIXME implement a better test for opterons"
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uint32_t nbcap;
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nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
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return !!(nbcap & NBCAP_128Bit);
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@ -1122,22 +1123,6 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
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set_dimm_size(ctrl, sz, i);
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}
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}
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static void fill_last(unsigned long node_id,unsigned long base)
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{
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//BY LYH //Fill next base reg with right value
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unsigned i;
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unsigned base_reg;
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base &=0xffff0000;
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device_t device;
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for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
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+= PCI_DEV(0, 1, 0)) {
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for(i=node_id+1;i<=7;i++) {
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base_reg=0x40+(i<<3);
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pci_write_config32(device,base_reg,base);
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}
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}
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//BY LYH END
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}
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static void route_dram_accesses(const struct mem_controller *ctrl,
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unsigned long base_k, unsigned long limit_k)
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@ -1148,8 +1133,8 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
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unsigned base;
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unsigned index;
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unsigned limit_reg, base_reg;
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device_t device;
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node_id = ctrl->node_id;
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index = (node_id << 3);
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limit = (limit_k << 2);
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@ -1166,7 +1151,6 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
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pci_write_config32(device, limit_reg, limit);
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pci_write_config32(device, base_reg, base);
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}
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}
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static void set_top_mem(unsigned tom_k)
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@ -1207,17 +1191,6 @@ static void order_dimms(const struct mem_controller *ctrl)
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/* Compute the memory base address address */
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base_k = 0;
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for(node_id = 0; node_id < ctrl->node_id; node_id++) {
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uint32_t limit, base;
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unsigned index;
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index = node_id << 3;
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base = pci_read_config32(ctrl->f1, 0x40 + index);
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/* Only look at the limit if the base is enabled */
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if ((base & 3) == 3) {
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limit = pci_read_config32(ctrl->f1, 0x44 + index);
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base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
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}
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}
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/* Remember which registers we have used in the high 8 bits of tom */
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tom = base_k >> 15;
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for(;;) {
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@ -1257,30 +1230,11 @@ static void order_dimms(const struct mem_controller *ctrl)
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/* Remember the dimm size */
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size = csbase >> 21;
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/* If this is the first chip select, round base_k to
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* be a multiple of it's size. Then set tom to equal
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* base_k.
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* I assume that size is a power of two.
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*/
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if ((tom & 0xff000000) == 0) {
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unsigned size_k;
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size_k = size << 15;
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base_k = (base_k + size_k -1) & ~(size_k -1);
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tom = base_k >> 15;
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}
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/* Remember I have used this register */
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tom |= (1 << (canidate + 24));
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/* Recompute the cs base register value */
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#if 1 // BY LYH Need to count from 0 for every memory controller
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csbase = ((tom - (base_k>>15))<< 21) | 1;
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// print_debug("csbase=");
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// print_debug_hex32(csbase);
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// print_debug("\r\n");
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#else //BY LYH END
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csbase = (tom << 21) | 1;
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#endif
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/* Increment the top of memory */
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tom += size;
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@ -1297,6 +1251,21 @@ static void order_dimms(const struct mem_controller *ctrl)
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}
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tom_k = (tom & ~0xff000000) << 15;
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/* Compute the memory base address */
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base_k = 0;
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for(node_id = 0; node_id < ctrl->node_id; node_id++) {
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uint32_t limit, base;
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unsigned index;
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index = node_id << 3;
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base = pci_read_config32(ctrl->f1, 0x40 + index);
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/* Only look at the limit if the base is enabled */
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if ((base & 3) == 3) {
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limit = pci_read_config32(ctrl->f1, 0x44 + index);
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base_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
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}
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}
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tom_k += base_k;
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#if 0
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print_debug("tom: ");
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print_debug_hex32(tom);
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@ -1307,18 +1276,6 @@ static void order_dimms(const struct mem_controller *ctrl)
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print_debug("\r\n");
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#endif
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route_dram_accesses(ctrl, base_k, tom_k);
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//BY LYH
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fill_last(ctrl->node_id, tom_k<<2);
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//BY LYH END
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#if 0 //BY LYH
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dump_pci_device(PCI_DEV(0, 0x18, 1));
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// if(ctrl->node_id==1) {
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// pci_write_config32(ctrl->f2, DRAM_CSBASE, 0x00000001);
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// }
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#endif
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set_top_mem(tom_k);
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}
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@ -2267,9 +2224,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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print_debug_hex32(dcl);
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print_debug("\r\n");
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#endif
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#if 0
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dcl &= ~DCL_DimmEccEn;
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#endif
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#warning "FIXME set the ECC type to perform"
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#warning "FIXME initialize the scrub registers"
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#if 1
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@ -2303,7 +2257,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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} else {
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print_debug(" done\r\n");
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}
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#if 1
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#if 0
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if (dcl & DCL_DimmEccEn) {
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print_debug("Clearing memory: ");
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loops = 0;
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