mb/google/mancomb: Add initial I2C configuration

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
This commit is contained in:
Eric Lai 2021-04-08 11:48:30 +08:00 committed by Patrick Georgi
parent ec76ae082a
commit 8af6b57788
3 changed files with 26 additions and 0 deletions

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@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI

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@ -38,6 +38,9 @@ chip soc/amd/cezanne
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device domain 0 on
device ref gpp_bridge_0 on end # WLAN
device ref gpp_bridge_1 on end # SD

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@ -1,4 +1,25 @@
chip soc/amd/cezanne
device domain 0 on
end # domain
# I2C Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | memory SPD bus |
#| I2C2 | Codec |
#| I2C3 | H1/D2 TPM |
#+-------------------+---------------------------+
register "i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.early_init = true,
}"
register "i2c[2]" = "{
.speed = I2C_SPEED_FAST,
}"
register "i2c[3]" = "{
.speed = I2C_SPEED_FAST,
.early_init = true,
}"
end # chip soc/amd/cezanne