mb/google/mancomb: Add initial I2C configuration
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
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@ -10,6 +10,8 @@ config BOARD_SPECIFIC_OPTIONS
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select AMD_SOC_CONSOLE_UART
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select BOARD_ROMSIZE_KB_16384
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select DISABLE_SPI_FLASH_ROM_SHARING
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_HID
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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@ -38,6 +38,9 @@ chip soc/amd/cezanne
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.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12),
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}"
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register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
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GPIO_I2C2_SCL | GPIO_I2C3_SCL"
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device domain 0 on
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device ref gpp_bridge_0 on end # WLAN
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device ref gpp_bridge_1 on end # SD
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@ -1,4 +1,25 @@
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chip soc/amd/cezanne
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device domain 0 on
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end # domain
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# I2C Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | memory SPD bus |
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#| I2C2 | Codec |
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#| I2C3 | H1/D2 TPM |
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#+-------------------+---------------------------+
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register "i2c[0]" = "{
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.speed = I2C_SPEED_FAST,
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.early_init = true,
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}"
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register "i2c[2]" = "{
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.speed = I2C_SPEED_FAST,
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}"
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register "i2c[3]" = "{
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.speed = I2C_SPEED_FAST,
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.early_init = true,
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}"
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end # chip soc/amd/cezanne
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