mb/google/skyrim/var/markarth: Update devicetree setting
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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# SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/amd/mendocino
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device domain 0 on end
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device domain 0 on
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device ref gpp_bridge_1 on
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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end
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end # NVME
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device ref gpp_bridge_2 on
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# Required so the NVMe gets placed into D3 when entering S0i3.
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chip drivers/pcie/rtd3/device
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register "name" = ""NVME""
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device pci 00.0 on end
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end
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end # NVME
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device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
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device ref xhci_1 on # XHCI1 controller
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chip drivers/usb/acpi
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device ref xhci_1_root_hub on # XHCI1 root hub
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chip drivers/usb/acpi
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device ref usb3_port3 on # USB 3.1 port3
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))"
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device usb 3.1 on end
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end
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end # USB 3.1 port3
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end
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chip drivers/usb/acpi
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device ref usb2_port3 on # USB 2 port3
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))"
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device usb 2.1 on end
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end
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end # USB 2 port3
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end
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end # XHCI1 root hub
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end
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end # XHCI1 controller
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end # Internal GPP Bridge 0 to Bus A
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end # domain
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device ref i2c_0 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
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register "wake" = "GEVENT_20"
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register "detect" = "1"
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device i2c 15 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""SYNA0000""
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register "generic.cid" = ""ACPI0C50""
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
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register "generic.wake" = "GEVENT_20"
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register "generic.detect" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end # I2C0
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device ref i2c_1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN9004""
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)"
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register "generic.detect" = "1"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
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register "generic.enable_delay_ms" = "10"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"
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register "generic.reset_off_delay_ms" = "1"
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register "generic.reset_delay_ms" = "10"
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register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)"
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register "generic.stop_delay_ms" = "180"
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register "generic.stop_off_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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end
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end # I2C1
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device ref i2c_2 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/i2c/generic
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register "hid" = ""10EC1019""
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register "desc" = ""Realtek SPK AMP R""
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register "uid" = "1"
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device i2c 29 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""10EC1019""
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register "desc" = ""Realtek SPK AMP L""
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register "uid" = "2"
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register "probed" = "1"
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device i2c 2a on end
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end
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end # I2C2
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end # chip soc/amd/mendocino
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