From 8b11b2c4dfb6b25f71910f13d13e81a2b089a4cb Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 6 Oct 2015 10:51:10 -0700 Subject: [PATCH] tpm: acpi: Add support for TPM PIRQ With SPI TPMs there is no SERIRQ for interrupts, instead it is a PIRQ based interrupt. The TCG PC Client Platform TPM Profile Specification says it must be active low and shared. This can be enabled with the CONFIG_TPM_PIRQ option that will specify the interrupt vector to report for the TPM. BUG=chrome-os-partner:40635 BRANCH=none TEST=verify TPM interrupt functionality in /proc/interrupts on glados Change-Id: Iad3ced213d1fc5380c559f50c086206dc9f22534 Signed-off-by: Patrick Georgi Original-Commit-Id: abdd0b8ecdf51ff32ed8bfee0823bbc30d5d3d49 Original-Change-Id: If7d22dfcfcab95dbd4c9edbd8674fc8d948a62d2 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/304133 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12147 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/pc80/tpm/Kconfig | 8 ++++++++ src/drivers/pc80/tpm/acpi/tpm.asl | 30 ++++++++++++++++++++++-------- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index f6a79483dc..0e8a0203df 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -23,6 +23,14 @@ config TPM_TIS_BASE_ADDRESS Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2. +config TPM_PIRQ + hex + default 0 + depends on LPC_TPM + help + This can be used to specify a PIRQ to use instead of SERIRQ, + which is needed for SPI TPM interrupt support on x86. + config TPM_INIT_FAILURE_IS_FATAL bool default n diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl index 489fec7308..044ff84d07 100644 --- a/src/drivers/pc80/tpm/acpi/tpm.asl +++ b/src/drivers/pc80/tpm/acpi/tpm.asl @@ -63,15 +63,29 @@ Device (TPM) IVEC, 4, /* SERIRQ vector */ } - If (LGreater (IVEC, 0)) { - /* Update interrupt vector */ - CreateField (^IBUF, ^TIRQ._INT, 32, TVEC) - Store (IVEC, TVEC) + CreateField (^IBUF, ^TIRQ._INT, 32, TVEC) + CreateBitField (^IBUF, ^TIRQ._HE, TTYP) + CreateBitField (^IBUF, ^TIRQ._LL, TPOL) + CreateBitField (^IBUF, ^TIRQ._SHR, TSHR) - /* Update interrupt type and polarity */ - CreateBitField (^IBUF, ^TIRQ._HE, TTYP) - CreateBitField (^IBUF, ^TIRQ._LL, TPOL) - CreateBitField (^IBUF, ^TIRQ._SHR, TSHR) + If (LGreater (CONFIG_TPM_PIRQ, 0)) { + /* + * PIRQ: Update interrupt vector with configured PIRQ + */ + Store (CONFIG_TPM_PIRQ, TVEC) + + /* Active-Low Level-Triggered Shared */ + Store (One, TPOL) + Store (Zero, TTYP) + Store (One, TSHR) + + /* Merge IRQ with base address */ + Return (ConcatenateResTemplate (RBUF, IBUF)) + } ElseIf (LGreater (IVEC, 0)) { + /* + * SERIRQ: Update interrupt vector based on TPM register + */ + Store (IVEC, TVEC) If (LEqual (ITPL, 0x0)) { /* Active-High Level-Triggered Shared */