From 8b120a87c37c3667e8d19689500a1641fd98143e Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Tue, 10 Dec 2013 08:35:51 -0800
Subject: [PATCH] baytrail: allow SD card controller capabilities overrides
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The SD card controller can have the capabilities it supports
to be overridden. Add two optional fields to the chip structure
to allow the mainboard to override the SD card controller
capabilities.

BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. Noted capabilities override console output.

Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4997
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
---
 src/soc/intel/baytrail/Makefile.inc |  1 +
 src/soc/intel/baytrail/chip.h       |  4 ++
 src/soc/intel/baytrail/sd.c         | 65 +++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+)
 create mode 100644 src/soc/intel/baytrail/sd.c

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 6485cc0aa4..48fb4b448a 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -43,6 +43,7 @@ ramstage-y += scc.c
 ramstage-y += emmc.c
 ramstage-y += lpss.c
 ramstage-y += pcie.c
+ramstage-y += sd.c
 
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 250f644cac..43a3efb650 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -51,6 +51,10 @@ struct soc_intel_baytrail_config {
 	/* LPE Audio Clock configuration. */
 	int lpe_codec_clk_freq; /* 19 or 25 are valid. */
 	int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
+
+	/* Native SD Card controller - override controller capabilities. */
+	uint32_t sdcard_cap_low;
+	uint32_t sdcard_cap_high;
 };
 
 extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
new file mode 100644
index 0000000000..82833c31c4
--- /dev/null
+++ b/src/soc/intel/baytrail/sd.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <reg_script.h>
+
+#include <baytrail/pci_devs.h>
+#include <baytrail/ramstage.h>
+#include "chip.h"
+
+#define CAP_OVERRIDE_LOW 0xa0
+#define CAP_OVERRIDE_HIGH 0xa4
+# define USE_CAP_OVERRIDES (1 << 31)
+
+static void sd_init(device_t dev)
+{
+	struct soc_intel_baytrail_config *config = dev->chip_info;
+
+	if (config == NULL)
+		return;
+
+	if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
+		printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
+		pci_write_config32(dev, CAP_OVERRIDE_LOW,
+		                   config->sdcard_cap_low);
+		pci_write_config32(dev, CAP_OVERRIDE_HIGH,
+		                   config->sdcard_cap_high | USE_CAP_OVERRIDES);
+	}
+}
+
+static const struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sd_init,
+	.enable			= NULL,
+	.scan_bus		= NULL,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+	.ops		= &device_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.device		= SD_DEVID,
+};