Add acpi tables and dsdt.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Tobias Diedrich
Rudolf Marek
parent
6222fe0443
commit
8b3cac2a6c
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@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select RAMINIT_SYSINFO
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select TINY_BOOTBLOCK
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select HAVE_PIRQ_TABLE
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select HAVE_ACPI_TABLES
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config MAINBOARD_DIR
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string
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@ -0,0 +1,196 @@
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/*
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* This file is part of the coreboot project.
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*
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* Written by Stefan Reinauer <stepan@openbios.org>.
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* ACPI FADT, FACS, and DSDT table support added by
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*
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* Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
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* Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
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* Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "southbridge/via/vt8237r/vt8237r.h"
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#include "southbridge/via/k8t890/k8t890.h"
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#include "northbridge/amd/amdk8/amdk8_acpi.h"
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#include <cpu/amd/model_fxx_powernow.h>
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extern const unsigned char AmlCode[];
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0);
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if (!dev)
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return current;
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res = find_resource(dev, K8T890_MMCONFIG_MBAR);
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if (res) {
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)
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current, res->base, 0x0, 0x0, 0xff);
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}
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return current;
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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unsigned int gsi_base = 0x18;
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/* Create all subtables for processors. */
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current = acpi_create_madt_lapics(current);
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/* Write SB IOAPIC. */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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VT8237R_APIC_ID, IO_APIC_ADDR, 0);
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/* Write NB IOAPIC. */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
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/* IRQ9 ACPI active low. */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
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/* IRQ0 -> APIC IRQ2. */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0x0);
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/* Create all subtables for processors. */
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current = acpi_create_madt_lapic_nmis(current,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
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return current;
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}
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unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
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{
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k8acpi_write_vars();
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amd_model_fxx_generate_powernow(0, 0, 0);
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return (unsigned long) (acpigen_get_current());
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}
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unsigned long write_acpi_tables(unsigned long start)
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{
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unsigned long current;
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acpi_rsdp_t *rsdp;
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acpi_srat_t *srat;
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acpi_rsdt_t *rsdt;
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acpi_mcfg_t *mcfg;
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acpi_hpet_t *hpet;
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acpi_madt_t *madt;
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acpi_fadt_t *fadt;
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acpi_facs_t *facs;
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acpi_slit_t *slit;
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acpi_header_t *ssdt;
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acpi_header_t *dsdt;
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/* Align ACPI tables to 16 byte. */
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start = (start + 0x0f) & -0x10;
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current = start;
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printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
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/* We need at least an RSDP and an RSDT table. */
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rsdp = (acpi_rsdp_t *) current;
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current += sizeof(acpi_rsdp_t);
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rsdt = (acpi_rsdt_t *) current;
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current += sizeof(acpi_rsdt_t);
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/* Clear all table memory. */
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memset((void *) start, 0, current - start);
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acpi_write_rsdp(rsdp, rsdt, NULL);
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acpi_write_rsdt(rsdt);
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/* We explicitly add these tables later on: */
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printk(BIOS_DEBUG, "ACPI: * FACS\n");
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/* we should align FACS to 64B as per ACPI specs */
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current = ALIGN(current, 64);
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facs = (acpi_facs_t *) current;
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current += sizeof(acpi_facs_t);
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acpi_create_facs(facs);
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dsdt = (acpi_header_t *) current;
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memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
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current += dsdt->length;
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memcpy(dsdt, &AmlCode, dsdt->length);
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dsdt->checksum = 0; /* Don't trust iasl to get this right. */
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dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
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dsdt->length);
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printk(BIOS_DEBUG, "ACPI: * FADT\n");
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fadt = (acpi_fadt_t *) current;
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current += sizeof(acpi_fadt_t);
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acpi_create_fadt(fadt, facs, dsdt);
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acpi_add_table(rsdp, fadt);
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printk(BIOS_DEBUG, "ACPI: * HPET\n");
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hpet = (acpi_hpet_t *) current;
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current += sizeof(acpi_hpet_t);
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acpi_create_hpet(hpet);
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acpi_add_table(rsdp, hpet);
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/* If we want to use HPET timers Linux wants an MADT. */
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printk(BIOS_DEBUG, "ACPI: * MADT\n");
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madt = (acpi_madt_t *) current;
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acpi_create_madt(madt);
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current += madt->header.length;
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acpi_add_table(rsdp, madt);
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printk(BIOS_DEBUG, "ACPI: * MCFG\n");
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mcfg = (acpi_mcfg_t *) current;
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acpi_create_mcfg(mcfg);
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current += mcfg->header.length;
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acpi_add_table(rsdp, mcfg);
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printk(BIOS_DEBUG, "ACPI: * SRAT\n");
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srat = (acpi_srat_t *) current;
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acpi_create_srat(srat);
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current += srat->header.length;
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acpi_add_table(rsdp, srat);
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/* SLIT */
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printk(BIOS_DEBUG, "ACPI: * SLIT\n");
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slit = (acpi_slit_t *) current;
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acpi_create_slit(slit);
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current+=slit->header.length;
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acpi_add_table(rsdp,slit);
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/* SSDT */
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printk(BIOS_DEBUG, "ACPI: * SSDT\n");
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ssdt = (acpi_header_t *)current;
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acpi_create_ssdt_generator(ssdt, "DYNADATA");
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current += ssdt->length;
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acpi_add_table(rsdp, ssdt);
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printk(BIOS_INFO, "ACPI: done.\n");
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return current;
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}
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@ -0,0 +1,534 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* ISA portions taken from QEMU acpi-dsdt.dsl.
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*/
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#define LNKA INTA
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#define LNKB INTB
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#define LNKC INTC
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#define LNKD INTD
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/*
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* For simplicity map LNK[E-H] to LNK[A-D].
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* This also means we are 82C596 compatible.
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* Needs 0:11.0 0x46[4] set to 0.
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*/
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#define LNKE INTA
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#define LNKF INTB
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#define LNKG INTC
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#define LNKH INTD
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DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
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{
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Name(APIC, 0) // 0=>8259, 1=>IOAPIC
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, APIC)
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}
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/* _PR CPU0 is dynamically supplied by SSDT */
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/* For now only define 2 power states:
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* - S0 which is fully on
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* - S5 which is soft off
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* Any others would involve declaring the wake up methods.
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*
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* Package contents:
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* ofs len desc
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* 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system state.
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* 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any
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* given state, OSPM must write the PM1a_CNT.SLP_TYP register before the
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* PM1b_CNT.SLP_TYP register.
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* 2 2 Reserved
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*/
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Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
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Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
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/* Root of the bus hierarchy */
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Scope (\_SB)
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{
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/* Top PCI device */
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Device (PCI0)
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{
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00180000)
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Name (_BBN, 0x00)
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Name (APRT, Package() {
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/* AGP? */
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Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
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Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
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Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
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Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
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/* PCIe graphics bridge */
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Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
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Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
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/* PCIe bridge */
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Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
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Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
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Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
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Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
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/* SATA */
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Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
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/* IDE */
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Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
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/* USB */
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Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
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Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
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Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
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Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
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/* PCI bridge */
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Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
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Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
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})
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Name (PPRT, Package() {
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/* ?? */
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Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
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/* PCIe graphics bridge */
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Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
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/* PCIe bridge */
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Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
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/* SATA */
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Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
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/* USB */
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Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
|
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Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
|
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Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
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Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
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/* PCI bridge */
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Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
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Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
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})
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/* PCI Routing Table */
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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|
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Device (PEGG)
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{
|
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Name (_ADR, 0x00020000)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
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})
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Method (_PRT, 0, NotSerialized)
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{
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If (APIC)
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{
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Return (APRT)
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}
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Return (PPRT)
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}
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}
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Device (PEX0)
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{
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Name (_ADR, 0x00030000)
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Name (APRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
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Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
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Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
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Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
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})
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Name (PPRT, Package () {
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Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
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Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
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||||
Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (APIC)
|
||||
{
|
||||
Return (APRT)
|
||||
}
|
||||
Return (PPRT)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PEX1)
|
||||
{
|
||||
Name (_ADR, 0x00030001)
|
||||
Name (APRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
|
||||
})
|
||||
Name (PPRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (APIC)
|
||||
{
|
||||
Return (APRT)
|
||||
}
|
||||
Return (PPRT)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PEX2)
|
||||
{
|
||||
Name (_ADR, 0x00030002)
|
||||
Name (APRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
|
||||
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
|
||||
})
|
||||
Name (PPRT, Package () {
|
||||
Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
|
||||
Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (APIC)
|
||||
{
|
||||
Return (APRT)
|
||||
}
|
||||
Return (PPRT)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PCI6)
|
||||
{
|
||||
Name (_ADR, 0x00130000)
|
||||
Name (APRT, Package () {
|
||||
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
|
||||
})
|
||||
Name (PPRT, Package () {
|
||||
Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
|
||||
})
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (APIC)
|
||||
{
|
||||
Return (APRT)
|
||||
}
|
||||
Return (PPRT)
|
||||
}
|
||||
}
|
||||
|
||||
Device (PCI7)
|
||||
{
|
||||
Name (_ADR, 0x00130001)
|
||||
Name (APRT, Package () {
|
||||
/* PCI slot 1 */
|
||||
Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
|
||||
|
||||
/* PCI slot 2 */
|
||||
Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
|
||||
|
||||
/* PCI slot 3 */
|
||||
Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
|
||||
Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
|
||||
|
||||
/* PCI slot 4 */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
|
||||
Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
|
||||
Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
|
||||
Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
|
||||
})
|
||||
Name (PPRT, Package () {
|
||||
/* PCI slot 1 */
|
||||
Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
|
||||
|
||||
/* PCI slot 2 */
|
||||
Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
|
||||
Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
|
||||
|
||||
/* PCI slot 3 */
|
||||
Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
|
||||
Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
|
||||
Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
|
||||
|
||||
/* PCI slot 4 */
|
||||
Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
|
||||
Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
|
||||
Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
|
||||
Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
|
||||
})
|
||||
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (APIC)
|
||||
{
|
||||
Return (APRT)
|
||||
}
|
||||
Return (PPRT)
|
||||
}
|
||||
}
|
||||
|
||||
Device (SBRG) { /* southbridge */
|
||||
Name (_ADR, 0x00110000)
|
||||
|
||||
/* PS/2 keyboard (seems to be important for WinXP install) */
|
||||
Device (KBD)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
|
||||
IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
|
||||
IRQNoFlags () {1}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* PS/2 mouse */
|
||||
Device (MOU)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IRQNoFlags () {12}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
|
||||
/* Parallel port */
|
||||
Device (LPT0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0401"))
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0f)
|
||||
}
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (TMP, ResourceTemplate () {
|
||||
IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
|
||||
IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
|
||||
IRQNoFlags () {7}
|
||||
DMA (Compatibility, NotBusMaster, Transfer8) {3}
|
||||
})
|
||||
Return (TMP)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
External(TOM1) /* top of memory below 4GB */
|
||||
|
||||
Method(_CRS, 0) {
|
||||
Name(TMP, ResourceTemplate() {
|
||||
WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
0x0000, // Granularity
|
||||
0x0000, // Range Minimum
|
||||
0x00FF, // Range Maximum
|
||||
0x0000, // Translation Offset
|
||||
0x0100, // Length
|
||||
,,
|
||||
)
|
||||
IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
|
||||
|
||||
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, /* address granularity */
|
||||
0x0000, /* range minimum */
|
||||
0x0CF7, /* range maximum */
|
||||
0x0000, /* translation */
|
||||
0x0CF8 /* length */
|
||||
)
|
||||
|
||||
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, /* address granularity */
|
||||
0x0D00, /* range minimum */
|
||||
0xFFFF, /* range maximum */
|
||||
0x0000, /* translation */
|
||||
0xF300 /* length */
|
||||
)
|
||||
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
})
|
||||
CreateDWordField(TMP, MMIO._BAS, MM1B)
|
||||
CreateDWordField(TMP, MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
*
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
|
||||
Return(TMP)
|
||||
}
|
||||
}
|
||||
|
||||
OperationRegion (PCI0.SBRG.SBR1, PCI_Config, 0x55, 0x03)
|
||||
Field (PCI0.SBRG.SBR1, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
/*
|
||||
* Offset 0x55:
|
||||
* 3-0: reserved
|
||||
* 7-4: PCI INTA# routing
|
||||
* Offset 0x56:
|
||||
* 3-0: PCI INTB# routing
|
||||
* 7-4: PCI INTC# routing
|
||||
* Offset 0x57:
|
||||
* 3-0: reserved
|
||||
* 7-4: PCI INTD# routing
|
||||
*
|
||||
* Valid values for routing link:
|
||||
* 0: disabled
|
||||
* 2,8,13: reserved
|
||||
* 1,3-7,9-12,14,15: corresponding irq
|
||||
*/
|
||||
, 4,
|
||||
PINA, 4,
|
||||
PINB, 4,
|
||||
PINC, 4,
|
||||
, 4,
|
||||
PIND, 4,
|
||||
}
|
||||
|
||||
Name(IRQB, ResourceTemplate(){
|
||||
IRQ(Level,ActiveLow,Shared){15}
|
||||
})
|
||||
|
||||
Name(IRQP, ResourceTemplate(){
|
||||
IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
|
||||
})
|
||||
|
||||
/* adapted from ma78gm/dsdt.asl */
|
||||
#define PCI_INTX_DEV(intx, pinx, uid) \
|
||||
Device(intx) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
\
|
||||
Method(_STA, 0) { \
|
||||
if (pinx) { \
|
||||
Return(0x0B) \
|
||||
} \
|
||||
Return(0x09) \
|
||||
} \
|
||||
\
|
||||
Method(_DIS ,0) { \
|
||||
Store(0, pinx) \
|
||||
} \
|
||||
\
|
||||
Method(_PRS ,0) { \
|
||||
Return(IRQP) \
|
||||
} \
|
||||
\
|
||||
Method(_CRS ,0) { \
|
||||
CreateWordField(IRQB, 1, IRQN) \
|
||||
ShiftLeft(1, pinx, IRQN) \
|
||||
Return(IRQB) \
|
||||
} \
|
||||
\
|
||||
Method(_SRS, 1) { \
|
||||
CreateWordField(ARG0, 1, IRQM) \
|
||||
\
|
||||
/* Use lowest available IRQ */ \
|
||||
FindSetRightBit(IRQM, Local0) \
|
||||
if (Local0) { \
|
||||
Decrement(Local0) \
|
||||
} \
|
||||
Store(Local0, pinx) \
|
||||
} \
|
||||
} \
|
||||
|
||||
PCI_INTX_DEV(INTA, PINA, 1)
|
||||
PCI_INTX_DEV(INTB, PINB, 2)
|
||||
PCI_INTX_DEV(INTC, PINC, 3)
|
||||
PCI_INTX_DEV(INTD, PIND, 4)
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue