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soc/intel/elkhartlake: Drop redundant PcieRpEnable 

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Nico Huber 2024-01-12 16:22:19 +01:00 committed by Felix Singer
parent 059476d18c
commit 8b4677fbbf
14 changed files with 26 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
View File

@ -42,14 +42,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "0x00"
register "PcieClkSrcUsage[1]" = "0x06"
register "PcieClkSrcUsage[2]" = "0x04"

6
src/mainboard/protectli/vault_ehl/devicetree.cb
View File

@ -43,12 +43,6 @@ chip soc/intel/elkhartlake
register "usb3_ports[3]" = "USB3_PORT_EMPTY"
# PCIe root ports related UPDs
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"

3
src/mainboard/siemens/fa_ehl/variants/fa_ehl/devicetree.cb
View File

@ -40,9 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"

6
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
View File

@ -40,12 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"

3
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
View File

@ -40,9 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"

4
src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
View File

@ -40,10 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"

6
src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
View File

@ -40,12 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"

3
src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
View File

@ -40,9 +40,6 @@ chip soc/intel/elkhartlake
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"

2
src/soc/intel/elkhartlake/Makefile.inc
View File

@ -22,6 +22,7 @@ bootblock-y += p2sb.c
romstage-y += espi.c
romstage-y += gpio.c
romstage-y += meminit.c
romstage-y += pcie_rp.c
romstage-y += reset.c
ramstage-y += acpi.c
@ -33,6 +34,7 @@ ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
ramstage-y += pcie_rp.c
ramstage-y += pmc.c
ramstage-y += reset.c
ramstage-y += systemagent.c

6
src/soc/intel/elkhartlake/chip.c
View File

@ -14,14 +14,10 @@
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
#include <soc/pcie.h>
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
static const struct pcie_rp_group pch_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 7, .lcap_port_base = 1 },
{ 0 }
};
#if CONFIG(HAVE_ACPI_TABLES)
const char *soc_acpi_name(const struct device *dev)
{

1
src/soc/intel/elkhartlake/chip.h
View File

@ -212,7 +212,6 @@ struct soc_intel_elkhartlake_config {
uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices.

10
src/soc/intel/elkhartlake/include/soc/pcie.h Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_ELKHARTLAKE_PCIE_H__
#define __SOC_ELKHARTLAKE_PCIE_H__
#include <intelblocks/pcie_rp.h>
extern const struct pcie_rp_group pch_rp_groups[];
#endif /* __SOC_ELKHARTLAKE_PCIE_H__ */

10
src/soc/intel/elkhartlake/pcie_rp.c Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/pcie_rp.h>
#include <soc/pci_devs.h>
#include <soc/pcie.h>
const struct pcie_rp_group pch_rp_groups[] = {
{ .slot = PCH_DEV_SLOT_PCIE, .count = 7, .lcap_port_base = 1 },
{ 0 }
};

13
src/soc/intel/elkhartlake/romstage/fsp_params.c
View File

@ -5,8 +5,10 @@
#include <device/device.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pcie_rp.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pcie.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
@ -19,9 +21,6 @@ enum {
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_elkhartlake_config *config)
{
unsigned int i;
uint32_t mask = 0;
/*
* If IGD is enabled, set IGD stolen size to 60MB.
* Otherwise, skip IGD init in FSP.
@ -33,13 +32,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
/* PCIe root port configuration */
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);