soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
Copy the AES-NI locking function to common cpu code to be able to reuse it. This change only copies the code and adds the MSR header file. Any further rework and later deduplication on the platforms code is done in the follow-up changes. Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -27,4 +27,10 @@ bool intel_ht_supported(void);
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*/
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bool intel_ht_sibling(void);
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/*
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* Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
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* as suggested in Intel document 325384-070US.
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*/
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void set_aesni_lock(void);
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#endif
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@ -3,6 +3,7 @@
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#include <acpi/acpigen.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <cpu/intel/msr.h>
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#include <cpu/x86/msr.h>
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#include "common.h"
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@ -264,3 +265,22 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
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config->regs[CPPC_AUTO_SELECT] = msr;
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}
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}
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/*
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* Lock AES-NI feature (MSR_FEATURE_CONFIG) to prevent unintended disabling
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* as suggested in Intel document 325384-070US.
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*/
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void set_aesni_lock(void)
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{
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msr_t msr;
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/* Only run once per core as specified in the MSR datasheet */
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if (intel_ht_sibling())
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return;
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msr = rdmsr(MSR_FEATURE_CONFIG);
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if ((msr.lo & 1) == 0) {
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msr.lo |= 1;
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wrmsr(MSR_FEATURE_CONFIG, msr);
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}
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}
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@ -0,0 +1,11 @@
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#ifndef CPU_INTEL_MSR_H
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#define CPU_INTEL_MSR_H
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/*
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* Common MSRs for Intel CPUs
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*/
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#define MSR_FEATURE_CONFIG 0x13c
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#define AESNI_LOCK_BIT 0
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#endif /* CPU_INTEL_MSR_H */
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